ZHCSS23A april   2023  – august 2023 LMH32401-Q1

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 绝对最大额定值
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: Gain = 2 kΩ
    6. 6.6 Electrical Characteristics: Gain = 20 kΩ
    7. 6.7 Electrical Characteristics: Both Gains
    8. 6.8 Electrical Characteristics: Logic Threshold and Switching Characteristics
    9. 6.9 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Switched Gain Transimpedance Amplifier
      2. 7.3.2 Clamping and Input Protection
      3. 7.3.3 ESD Protection
      4. 7.3.4 Differential Output Stage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Ambient Light Cancellation (ALC) Mode
      2. 7.4.2 Power-Down Mode (Multiplexer Mode)
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 接收文档更新通知
    4. 9.4 支持资源
    5. 9.5 Trademarks
    6. 9.6 静电放电警告
    7. 9.7 术语表
  11. 10Mechanical, Packaging, and Orderable Information

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Differential Output Stage

The differential output stage of the LMH32401-Q1 performs the following two functions, which are common across all differential amplifiers:

  1. Converts the single-ended output from the TIA stage to a differential output.
  2. Performs a common-mode output shift to match the specified ADC input common-mode voltage.

The differential output stage has two 10-Ω series resistors on the output to isolate the amplifier output stage transistors from the package bond-wire inductance and printed circuit board (PCB) capacitance. The net gain of the LMH32401-Q1 (TIA + output stage) is 2 kΩ (low gain) and 20 kΩ (high gain) when driving an external 100‑Ω resistor. When the external load resistor is increased above 100 Ω, the effective gain from the IN pin to the differential output pin increases. Conversely, when the external load resistor is decreased to less than 100 Ω, the effective gain from the IN pin to the differential output pin decreases as a result of the larger voltage drop across the two internal 10-Ω resistors. When there is no load resistor between the OUT+ and OUT– pins, the effective gain of the LMH32401-Q1 in the low-gain configuration is 2.4 kΩ, and in the high-gain configuration is 24 kΩ.

The output common-mode voltage of the LMH32401-Q1 is set externally through the VOCM pin. A resistor divider internal to the amplifier (between VDD2 and ground) sets the default voltage to 1.1 V. The internal resistors generate common-mode noise that is typically rejected by the CMRR of the subsequent ADC stage. To maximize the amplifier signal-to-noise ratio (SNR), place an external noise bypass capacitor to ground on the VOCM pin. In single-ended signal chains, such as ToF systems that use time-to-digital converters (TDCs), only a single output of the LMH32401-Q1 is required. In such situations, terminate the unused differential output in the same manner as the used output to maintain balance and symmetry. The signal swing of the single-ended output is half of the available differential output swing. Additionally, the common-mode noise of the output stage, which is typically rejected by the differential input ADC, is now added to the total noise, and further degrades SNR.

The output stage of the LMH32401-Q1 has an additional VOD input that sets the differential output between OUT– and OUT+. Figure 7-1 shows how each output pin of the LMH32401-Q1 is at the voltage set by the VOCM pin (default = 1.1 V) when the photodiode output current is zero and the VOD input is set to 0 V. When the VOD pin is driven to a voltage of X volts, the two output pins are separated by X volts when the photodiode current is zero. The average voltage is still equal to VOCM. For example, Figure 7-2 shows that if VOCM is set to 1.1 V and VOD is set to 0.4 V, then OUT– = 1.1 V + 0.2 V = 1.3 V and OUT+ = 1.1 V – 0.2 V = 0.9 V.

GUID-95E64B00-C340-4881-B5BF-376B91481982-low.gifFigure 7-1 Individual Single-ended Outputs With VOD = 0 V
GUID-AD34E3FE-5957-4310-A01B-6953731BF284-low.gifFigure 7-2 Individual Single-Ended Outputs With VOD = 0.4 V

The VOD pin is functional only when the LMH32401-Q1 is used with a PD that sinks the photocurrent. Set VOD = 0 V when the LMH32401-Q1 is interfaced with a PD that sources the photocurrent. The VOD output offset feature is included in the LMH32401-Q1 because the output current of a photodiode is unipolar. Depending on the reverse bias configuration, the photodiode can either sink or source current, but cannot do both simultaneously. With the anode connected to a negative bias and the cathode connected to the TIA stage input, the photodiode can only sink current, which implies that the TIA stage output swings in a positive direction greater than the default input bias voltage (2.47 V). Subsequently, OUT– only swings less than VOCM, and OUT+ only swings greater than VOCM. Figure 7-1 shows how the LMH32401-Q1 device only uses half of the output swing range (VOUT = VOUT+ – VOUT–) when VOD = 0 V because one output never swings less than VOCM and the other output never exceeds VOCM. The signal dynamic range in this case is 0.4 VPP – 0 V = 0.4 VPP.

Figure 7-2 shows how the VOD pin voltage allows OUT– to be level-shifted to greater than VOCM, and OUT+ to be level-shifted below VOCM to maximize the output swing capabilities of the amplifier. The signal dynamic range in this case is 0.4 VPP – (–0.4 VPP) = 0.8 VPP.

When the LMH32401-Q1 device drives a 100‑Ω load, the voltage set at the VOD pin is equal to the differential output offset (VOUT = VOUT+ – VOUT–) when the input signal current is zero. Use Equation 1 to calculate the differential output offset under other load conditions.

Equation 1. VOD=1.2 × VVOD×RLRL+20Ω

where

  • VVOD = Voltage applied at pin 9
  • VOD = (VOUT–) – (VOUT+)
  • RL = External load resistance