12.1 Layout Guidelines

With a GBP of 6.5 GHz, layout for the LMH5401-SP is critical and nothing can be neglected. In order to simplify board design, the LMH5401-SP has on-chip resistors that reduce the affect of off-chip capacitance. For this reason, TI recommends that the ground layer below the LMH5401-SP not be cut. The recommendation not to cut the ground plane under the amplifier input and output pins is different than many other high-speed amplifiers, but the reason is that parasitic inductance is more harmful to the LMH5401-SP performance than parasitic capacitance. By leaving the ground layer under the device intact, parasitic inductance of the output and power traces is minimized. The DUT portion of the evaluation board layout is illustrated in Figure 78.

The EVM uses long-edge capacitors for the decoupling capacitors, which reduces series resistance and increases the resonant frequency. Vias are also placed to the power planes before the bypass capacitors. Although not evident in the top layer, two vias are used at the capacitor in addition to the two vias underneath the device.

The output matching resistors are 0402 size and are placed very close to the amplifier output pins, which reduces both parasitic inductance and capacitance. The use of 0603 output matching resistors produces a measurable decrease in bandwidth.

When the signal is on a 50-Ω controlled impedance transmission line, the layout then becomes much less critical. The transition from the 50-Ω transmission line to the amplifier pins is the most critical area.

The CM pin also requires a bypass capacitor. Place this capacitor near the device. Refer to the user guide LMH5401EVM-CVAL evaluation module, (SLOU478) for more details on board layout and design.