As can be seen in the schematic of Figure 6-2, a small capacitor is inserted in parallel with the series input resistors. The reason for this is to compensate for the natural band-limiting effect of the 1st order filter formed by this resistor and the input capacitance of the buffer. With a typical C_IN of 3.5 pF (Figure 6-2), a pole is created at

This will band-limit the buffer and produce further phase lag. If used in an op amp-loop application with an amplifier that has the same order of magnitude of unity gain crossing as fp2, this additional phase lag will produce oscillation.

The solution is to add a small feed-forward capacitor (phase lead) around the input resistor, as shown in Figure 6-2. The value of this capacitor is not critical but should be such that the time constant formed by it and the input resistor that it is in parallel with (R_IN) be at least five times the time constant of R_INC_IN. Therefore,

from Section 5.4, R_IN is 250 kΩ.

In the case of the example in Figure 6-2, R_INC_IN produces a time-constant of 870 ns, so C₁ should be chosen to be a minimum of 4.4 μs, or 438 pF. The value of C₁ (1000 pF) shown in Figure 6-2 gives 10 μs.