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SNOS966Q May 2001 – September 2014 LMH6642 , LMH6643 , LMH6644

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

PW|14
- MPDS360A
D|14
- MPDS177H

散热焊盘机械数据 (封装 | 引脚)

订购信息

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾⁽²⁾

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_INDifferential			±2.5	V
Output Short Circuit Duration		See ⁽⁴⁾ and ⁽⁶⁾
Supply Voltage (V⁺ - V⁻)			13.5	V
Voltage at Input/Output pins			V⁺ +0.8 V⁻ −0.8	V
Input Current			±10	mA
Junction Temperature⁽⁵⁾			+150	°C
Soldering Information	Infrared or Convection Reflow (20 sec)		235	°C
Soldering Information	Wave Soldering Lead Temp.(10 sec)		260	°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics.

(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.

(3) Human body model, 1.5 kΩ in series with 100 pF. Machine Model, 0 Ω in series with 200 pF.

(4) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C.

(5) The maximum power dissipation is a function of T_J(MAX), R_θJA, and T_A. The maximum allowable power dissipation at any ambient temperature is P_D = (T_J(MAX) - T_A)/ R_θJA . All numbers apply for packages soldered directly onto a PC board.

7.2 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage temperature range		−65	+150	°C
V_(ESD)	Electrostatic discharge⁽³⁾	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾		2000	V
		Machine model (MM)⁽³⁾		200
		Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾		1000

(1) JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 1000-V CDM allows safe manufacturing with a standard ESD control process.

(3) JEDEC document JEP157 states that 200-V MM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Supply Voltage (V⁺ – V⁻)		2.7	12.8	V
Operating Temperature Range⁽²⁾		−40	+85	°C

(2) The maximum power dissipation is a function of T_J(MAX), R_θJA, and T_A. The maximum allowable power dissipation at any ambient temperature is P_D = (T_J(MAX) - T_A)/ R_θJA. All numbers apply for packages soldered directly onto a PC board.

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		LMH6642		LMH6643	LMH6644		UNIT
		DBV05A	D08A	DGK08A	D14A	PW14A
		5 PINS	8 PINS	8 PINS	14 PINS	14 PINS
R_θJA	Junction-to-ambient Thermal Resistance⁽²⁾	265	190	235	145	155	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 3V Electrical Characteristics

Unless otherwise specified, all limits ensured for V⁺ = 3V, V⁻ = 0V, V_CM = V_O = V⁺/2, V_ID (input differential voltage) as noted (where applicable) and R_L = 2kΩ to V⁺/2.

	PARAMETER	TEST CONDITIONS	AT TEMPERATURE EXTREMES			V⁺ = 3V, V⁻ = 0V, V_CM = V_O = V⁺/2, V_ID R_L = 2 kΩ to V⁺/2			UNIT
	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	MIN⁽¹⁾	TYP⁽²⁾	MAX⁽¹⁾	UNIT
BW	−3dB BW	A_V = +1, V_OUT = 200mV_PP				80	115		MHz
BW	−3dB BW	A_V = +2, −1, V_OUT = 200mV_PP					46		MHz
BW_0.1dB	0.1dB Gain Flatness	A_V = +2, R_L = 150Ω to V+/2, Rf = 402Ω, V_OUT = 200mV_PP					19		MHz
PBW	Full Power Bandwidth	A_V = +1, −1dB, V_OUT = 1V_PP					40		MHz
e_n	Input-Referred Voltage Noise	f = 100kHz					17		nV/√Hz
e_n	Input-Referred Voltage Noise	f = 1kHz					48		nV/√Hz
i_n	Input-Referred Current Noise	f = 100kHz					0.90		pA/√Hz
i_n	Input-Referred Current Noise	f = 1kHz					3.3		pA/√Hz
THD	Total Harmonic Distortion	f = 5MHz, V_O = 2V_PP, A_V = −1, R_L = 100Ω to V⁺/2					−48		dBc
DG	Differential Gain	V_CM = 1V, NTSC, A_V = +2 R_L =150Ω to V⁺/2					0.17%
DG	Differential Gain	R_L =1kΩ to V⁺/2					0.03%
DP	Differential Phase	V_CM = 1V, NTSC, A_V = +2 R_L =150Ω to V⁺/2					0.05		deg
DP	Differential Phase	R_L =1kΩ to V⁺/2					0.03		deg
CT Rej.	Cross-Talk Rejection	f = 5MHz, Receiver: R_f = R_g = 510Ω, A_V = +2					47		dB
T_S	Settling Time	V_O = 2V_PP, ±0.1%, 8pF Load, V_S = 5V					68		ns
SR	Slew Rate ⁽³⁾	A_V = −1, V_I = 2V_PP				90	120		V/µs
V_OS	Input Offset Voltage	For LMH6642 and LMH6644			±7		±1	±5	mV
V_OS	Input Offset Voltage	For LMH6643			±7		±1	±3.4	mV
TC V_OS	Input Offset Average Drift	See ⁽⁴⁾					±5		µV/°C
I_B	Input Bias Current	See ⁽⁵⁾			−3.25		−1.50	−2.60	µA
I_OS	Input Offset Current				1000		20	800	nA
R_IN	Common Mode Input Resistance						3		MΩ
C_IN	Common Mode Input Capacitance						2		pF
CMVR	Input Common-Mode Voltage Range	CMRR ≥ 50dB			−0.1		−0.5	−0.2	V
CMVR	Input Common-Mode Voltage Range	CMRR ≥ 50dB	1.6			1.8	2.0		V
CMRR	Common Mode Rejection Ratio	V_CM Stepped from 0V to 1.5V				72	95		dB
A_VOL	Large Signal Voltage Gain	V_O = 0.5V to 2.5V R_L = 2kΩ to V⁺/2	75			80	96		dB
A_VOL	Large Signal Voltage Gain	V_O = 0.5V to 2.5V R_L = 150Ω to V⁺/2	70			74	82		dB
V_O	Output Swing High	R_L = 2kΩ to V⁺/2, V_ID = 200mV				2.90	2.98		V
	Output Swing High	R_L = 150Ω to V⁺/2, V_ID = 200mV				2.80	2.93		V
	Output Swing Low	R_L = 2kΩ to V⁺/2, V_ID = −200mV					25	75	mV
	Output Swing Low	R_L = 150Ω to V⁺/2, V_ID = −200mV					75	150	mV
I_SC	Output Short Circuit Current	Sourcing to V⁺/2 V_ID = 200mV ⁽⁶⁾	35			50	95		mA
I_SC	Output Short Circuit Current	Sinking to V⁺/2 V_ID = −200mV ⁽⁶⁾	40			55	110		mA
I_OUT	Output Current	V_OUT = 0.5V from either supply					±65		mA
+PSRR	Positive Power Supply Rejection Ratio	V⁺ = 3.0V to 3.5V, V_CM = 1.5V				75	85		dB
I_S	Supply Current (per channel)	No Load			4.50		2.70	4.00	mA

(1) All limits are ensured by testing or statistical analysis.

(2) Typical values represent the most likely parametric norm.

(3) Slew rate is the average of the rising and falling slew rates.

(4) Offset voltage average drift determined by dividing the change in V_OS at temperature extremes by the total temperature change.

(5) Positive current corresponds to current flowing into the device.

(6) Short circuit test is a momentary test. See ^{Note 7} under 5 V Electrical Characteristics.

7.6 5V Electrical Characteristics

Unless otherwise specified, all limits ensured for V⁺ = 5V, V⁻ = 0V, V_CM = V_O = V⁺/2, V_ID (input differential voltage) as noted (where applicable) and R_L = 2kΩ to V⁺/2.

	PARAMETER	TEST CONDITIONS	AT TEMPERATURE EXTREMES			V⁺ = 5V, V⁻ = 0V, V_CM = V_O = V⁺/2, V_ID R_L = 2kΩ to V⁺/2			UNIT
	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	MIN⁽¹⁾	TYP⁽²⁾	MAX⁽¹⁾	UNIT
BW	−3dB BW	A_V = +1, V_OUT = 200mV_PP				90	120		MHz
BW	−3dB BW	A_V = +2, −1, V_OUT = 200mV_PP					46		MHz
BW_0.1dB	0.1dB Gain Flatness	A_V = +2, R_L = 150Ω to V+/2, R_f = 402Ω, V_OUT = 200mV_PP					15		MHz
PBW	Full Power Bandwidth	A_V = +1, −1dB, V_OUT = 2V_PP					22		MHz
e_n	Input-Referred Voltage Noise	f = 100kHz					17		nV/√Hz
e_n	Input-Referred Voltage Noise	f = 1kHz					48		nV/√Hz
i_n	Input-Referred Current Noise	f = 100kHz					0.90		pA/√Hz
i_n	Input-Referred Current Noise	f = 1kHz					3.3		pA/√Hz
THD	Total Harmonic Distortion	f = 5MHz, V_O = 2V_PP, A_V = +2					−60		dBc
DG	Differential Gain	NTSC, A_V = +2 R_L =150Ω to V⁺/2					0.16%
DG	Differential Gain	R_L = 1kΩ to V⁺/2					0.05%
DP	Differential Phase	NTSC, A_V = +2 R_L = 150Ω to V⁺/2					0.05		deg
DP	Differential Phase	R_L = 1kΩ to V⁺/2					0.01		deg
CT Rej.	Cross-Talk Rejection	f = 5MHz, Receiver: R_f = R_g = 510Ω, A_V = +2					47		dB
T_S	Settling Time	V_O = 2V_PP, ±0.1%, 8pF Load					68		ns
SR	Slew Rate ⁽³⁾	A_V = −1, V_I = 2V_PP				95	125		V/µs
V_OS	Input Offset Voltage	For LMH6642 and LMH6644			±7		±1	±5	mV
V_OS	Input Offset Voltage	For LMH6643			±7		±1	±3.4	mV
TC V_OS	Input Offset Average Drift	See ⁽⁴⁾					±5		µV/°C
I_B	Input Bias Current	See ⁽⁵⁾			−3.25		−1.70	−2.60	µA
I_OS	Input Offset Current				1000		20	800	nA
R_IN	Common Mode Input Resistance						3		MΩ
C_IN	Common Mode Input Capacitance						2		pF
CMVR	Input Common-Mode Voltage Range	CMRR ≥ 50dB			−0.1		−0.5	−0.2	V
CMVR	Input Common-Mode Voltage Range	CMRR ≥ 50dB	3.6			3.8	4.0		V
CMRR	Common Mode Rejection Ratio	V_CM Stepped from 0V to 3.5V				72	95		dB
A_VOL	Large Signal Voltage Gain	V_O = 0.5V to 4.50V R_L = 2kΩ to V⁺/2	82			86	98		dB
A_VOL	Large Signal Voltage Gain	V_O = 0.5V to 4.25V R_L = 150Ω to V⁺/2	72			76	82		dB
V_O	Output Swing High	R_L = 2kΩ to V⁺/2, V_ID = 200mV				4.90	4.98		V
	Output Swing High	R_L = 150Ω to V⁺/2, V_ID = 200mV				4.65	4.90		V
	Output Swing Low	R_L = 2kΩ to V⁺/2, V_ID = −200mV					25	100	mV
	Output Swing Low	R_L = 150Ω to V⁺/2, V_ID = −200mV					100	150	mV
I_SC	Output Short Circuit Current	Sourcing to V⁺/2 V_ID = 200mV ⁽⁶⁾⁽⁷⁾	40			55	115		mA
I_SC	Output Short Circuit Current	Sinking to V⁺/2 V_ID = −200mV ⁽⁶⁾⁽⁷⁾	55			70	140		mA
I_OUT	Output Current	V_O = 0.5V from either supply					±70		mA
+PSRR	Positive Power Supply Rejection Ratio	V⁺ = 4.0V to 6V				79	90		dB
I_S	Supply Current (per channel)	No Load			5.00		2.70	4.25	mA

(1) All limits are ensured by testing or statistical analysis.

(2) Typical values represent the most likely parametric norm.

(3) Slew rate is the average of the rising and falling slew rates.

(4) Offset voltage average drift determined by dividing the change in V_OS at temperature extremes by the total temperature change.

(5) Positive current corresponds to current flowing into the device.

(6) Short circuit test is a momentary test. See ^{Note 7}.

(7) Output short circuit duration is infinite for V_S < 6V at room temperature and below. For V_S > 6V, allowable short circuit duration is 1.5ms.

7.7 ±5V Electrical Characteristics

Unless otherwise specified, all limits ensured for V⁺ = 5V, V⁻ = −5V, V_CM = V_O = 0V, V_ID (input differential voltage) as noted (where applicable) and R_L = 2kΩ to ground.

	PARAMETER	TEST CONDITIONS	AT TEMPERATURE EXTREMES			V⁺ = 5V, V⁻ = −5V, V_CM = V_O = 0V, V_ID			UNIT
	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	MIN⁽²⁾	TYP⁽¹⁾	MAX⁽²⁾	UNIT
BW	−3dB BW	A_V = +1, V_OUT = 200mV_PP				95	130		MHz
BW	−3dB BW	A_V = +2, −1, V_OUT = 200mV_PP					46		MHz
BW_0.1dB	0.1dB Gain Flatness	A_V = +2, R_L = 150Ω to V+/2, R_f = 806Ω, V_OUT = 200mV_PP					12		MHz
PBW	Full Power Bandwidth	A_V = +1, −1dB, V_OUT = 2V_PP					24		MHz
e_n	Input-Referred Voltage Noise	f = 100kHz					17		nV/√Hz
e_n	Input-Referred Voltage Noise	f = 1kHz					48		nV/√Hz
i_n	Input-Referred Current Noise	f = 100kHz					0.90		pA/√Hz
i_n	Input-Referred Current Noise	f = 1kHz					3.3		pA/√Hz
THD	Total Harmonic Distortion	f = 5MHz, V_O = 2V_PP, A_V = +2					−62		dBc
DG	Differential Gain	NTSC, A_V = +2 R_L = 150Ω to V⁺/2					0.15%
DG	Differential Gain	R_L = 1kΩ to V⁺/2					0.01%
DP	Differential Phase	NTSC, A_V = +2 R_L = 150Ω to V⁺/2					0.04		deg
DP	Differential Phase	R_L = 1kΩ to V⁺/2					0.01		deg
CT Rej.	Cross-Talk Rejection	f = 5MHz, Receiver: R_f = R_g = 510Ω, A_V = +2					47		dB
T_S	Settling Time	V_O = 2V_PP, ±0.1%, 8pF Load, V_S = 5V					68		ns
SR	Slew Rate ⁽⁴⁾	A_V = −1, V_I = 2V_PP				100	135		V/µs
V_OS	Input Offset Voltage	For LMH6642 and LMH6644			±7		±1	±5	mV
V_OS	Input Offset Voltage	For LMH6643			±7		±1	±3.4	mV
TC V_OS	Input Offset Average Drift	See ⁽⁷⁾					±5		µV/°C
I_B	Input Bias Current	See ⁽³⁾			−3.25		−1.60	−2.60	µA
I_OS	Input Offset Current				1000		20	800	nA
R_IN	Common Mode Input Resistance						3		MΩ
C_IN	Common Mode Input Capacitance						2		pF
CMVR	Input Common-Mode Voltage Range	CMRR ≥ 50dB			−5.1		−5.5	−5.2	V
CMVR	Input Common-Mode Voltage Range	CMRR ≥ 50dB	3.6			3.8	4.0		V
CMRR	Common Mode Rejection Ratio	V_CM Stepped from −5V to 3.5V				74	95		dB
A_VOL	Large Signal Voltage Gain	V_O = −4.5V to 4.5V, R_L = 2kΩ	84			88	96		dB
A_VOL	Large Signal Voltage Gain	V_O = −4.0V to 4.0V, R_L = 150Ω	74			78	82		dB
V_O	Output Swing High	R_L = 2kΩ, V_ID = 200mV				4.90	4.96		V
	Output Swing High	R_L = 150Ω, V_ID = 200mV				4.65	4.80		V
	Output Swing Low	R_L = 2kΩ, V_ID = −200mV					−4.96	−4.90	V
	Output Swing Low	R_L = 150Ω, V_ID = −200mV					−4.80	−4.65	V
I_SC	Output Short Circuit Current	Sourcing to Ground V_ID = 200mV ⁽⁵⁾⁽⁶⁾	35			60	115		mA
I_SC	Output Short Circuit Current	Sinking to Ground V_ID = −200mV ⁽⁵⁾⁽⁶⁾	65			85	145		mA
I_OUT	Output Current	V_O = 0.5V from either supply				±75			mA
PSRR	Power Supply Rejection Ratio	(V⁺, V⁻) = (4.5V, −4.5V) to (5.5V, −5.5V)				78	90		dB
I_S	Supply Current (per channel)	No Load			5.50		2.70	4.50	mA

(1) Typical values represent the most likely parametric norm.

(2) All limits are ensured by testing or statistical analysis.

(3) Positive current corresponds to current flowing into the device.

(4) Slew rate is the average of the rising and falling slew rates.

(5) Short circuit test is a momentary test. See ⁽⁶⁾.

(6) Output short circuit duration is infinite for V_S < 6V at room temperature and below. For V_S > 6V, allowable short circuit duration is 1.5ms.

(7) Offset voltage average drift determined by dividing the change in V_OS at temperature extremes by the total temperature change.

7.8 Typical Performance Characteristics

V⁺ = +5, V⁻ = −5V, R_F = R_L = 2 kΩ. Unless otherwise specified.

Figure 1. Closed Loop Frequency Response
for Various Supplies

Figure 3. Closed Loop Gain vs. Frequency
for Various Gain

Figure 5. Closed Loop Gain vs. Frequency
for Various Supplies

Figure 7. Large Signal Frequency Response

Figure 9. Closed Loop Frequency Response
for Various Supplies

Figure 11. V_OUT (V_PP) for THD < 0.5%

Figure 13. V_OUT (V_PP) for THD < 0.5%

Figure 15. Open Loop Gain/Phase
for Various Temperature

Figure 17. HD3 (dBc) vs. Output Swing

Figure 19. HD3 vs. Output Swing

Figure 21. Settling Time vs. Input Step Amplitude
(Output Slew and Settle Time)

Figure 23. V_OUT from V⁺ vs. I_SOURCE

Figure 25. V_OUT from V⁺ vs. I_SOURCE

Figure 27. Swing vs. V_S

Figure 29. Output Sinking Saturation Voltage vs. I_OUT

Figure 31. Closed Loop Output Impedance
vs. Frequency A_V = +1

Figure 33. CMRR vs. Frequency

Figure 35. V_OS vs. V_OUT (Typical Unit)

Figure 37. V_OS vs. V_S (for 3 Representative Units)

Figure 39. V_OS vs. V_S (for 3 Representative Units)

Figure 41. I_OS vs. V_S

Figure 43. I_S vs. V_S

Figure 45. Large Signal Step Response

Figure 47. Small Signal Step Response

Figure 49. Small Signal Step Response

Figure 51. Large Signal Step Response

Figure 53. Large Signal Step Response

Figure 2. Closed Loop Gain vs. Frequency
for Various Gain

Figure 4. Closed Loop Frequency Response
for Various Temperature

Figure 6. Closed Loop Frequency Response
for Various Temperature

Figure 8. Closed Loop Small Signal Frequency Response
for Various Supplies

Figure 10. ±0.1dB Gain Flatness
for Various Supplies

Figure 12. V_OUT (V_PP) for THD < 0.5%

Figure 14. Open Loop Gain/Phase
for Various Temperature

Figure 16. HD2 (dBc) vs. Output Swing

Figure 18. HD2 vs. Output Swing

Figure 20. THD (dBc) vs. Output Swing

Figure 22. Input Noise vs. Frequency

Figure 24. V_OUT from V⁻ vs. I_SINK

Figure 26. V_OUT from V⁻ vs. I_SINK

Figure 28. Short Circuit Current (to V_S/2) vs. V_S

Figure 30. Output Sourcing Saturation Voltage vs. I_OUT

Figure 32. PSRR vs. Frequency

Figure 34. Crosstalk Rejection vs. Frequency
(Output to Output)

Figure 36. V_OS vs. V_CM (Typical Unit)

Figure 38. V_OS vs. V_S (for 3 Representative Units)

Figure 40. I_B vs. V_S

Figure 42. I_S vs. V_CM

Figure 44. Small Signal Step Response

Figure 46. Large Signal Step Response

Figure 48. Small Signal Step Response

Figure 50. Small Signal Step Response

Figure 52. Large Signal Step Response