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SNOSA03H November 2002 – May 2016 LMH6702

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

D|8
- MSOI002K
DBV|5
- MPDS018T

散热焊盘机械数据 (封装 | 引脚)

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
V_S			±6.75	V
I_OUT			See⁽³⁾
Common mode input voltage			V⁻ to V⁺	V
Maximum junction temperature			150	°C
Storage temperature		−65	150	°C
Soldering information	Infrared or convection (20 s)		235	°C
Soldering information	Wave soldering (10 s)		260	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.

(3) The maximum output current (I_OUT) is determined by device power dissipation limitations.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Machine Model (MM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±200	V

(1) Human body model: 1.5 kΩ in series with 100 pF. JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 2000-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.

(2) Machine model: 0 Ω in series with 200 pF. JEDEC document JEP157 states that 200-V MM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 200-V MM is possible with the necessary precautions. Pins listed as ±200 V may actually have higher performance.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
Operating temperature			−40	85	°C
Nominal supply voltage			±4	±6	V

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical Characteristics tables.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		LMH6702		UNIT
		DBV (SOT-23)	D (SOIC)
		5 PINS	8 PINS
R_θJA	Junction-to-ambient thermal resistance	182	133	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	139	79	°C/W
R_θJB	Junction-to-board thermal resistance	40	73	°C/W
ψ_JT	Junction-to-top characterization parameter	28	28	°C/W
ψ_JB	Junction-to-board characterization parameter	40	73	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

6.5 Electrical Characteristics

at A_V = 2, V_S = ±5 V, R_L = 100 Ω, R_F = 237 Ω (unless otherwise noted)⁽¹⁾

	PARAMETER	TEST CONDITIONS		MIN⁽³⁾	TYP⁽⁴⁾	MAX⁽³⁾	UNIT
FREQUENCY DOMAIN PERFORMANCE
SSBW_SM	-3-dB Bandwidth	V_OUT = 0.5 V_PP			1700		MHz
SSBW_LG		V_OUT = 2 V_PP			720
LSBW_LG		V_OUT = 4 V_PP			480
SSBW_HG		V_OUT = 2 V_PP, A_V = +10			140
GF_0.1dB	0.1-dB gain flatness	V_OUT = 2 V_PP			120		MHz
LPD	Linear phase deviation	DC to 100 MHz			0.09		deg
DG	Differential gain	R_L =150 Ω, 3.58 MHz			0.024%
DG	Differential gain	R_L =150 Ω, 4.43 MHz			0.021%
DP	Differential phase	R_L = 150 Ω, 3.58 MHz			0.004		deg
DP	Differential phase	R_L = 150 Ω, 4.43 MHz			0.007		deg
TIME DOMAIN RESPONSE
t_R	Rise time	2-V Step, TRS			0.87		ns
t_R	Rise time	2-V Step, TRL			0.77		ns
t_F	Fall time	6-V Step, TRS			1.70		ns
t_F	Fall time	6-V Step, TRL			1.70		ns
OS	Overshoot	2-V Step			0%
SR	Slew rate	6 V_PP, 40% to 60%⁽²⁾			3100		V/µs
T_s	Settling time to 0.1%	2-V Step			13.4		ns
DISTORTION AND NOISE RESPONSE
HD2L	2^nd Harmonic distortion	2 V_PP, 5 MHz⁽⁷⁾ (SOT-23)			−100		dBc
HD2L		2 V_PP, 5 MHz⁽⁷⁾ (SOIC)			−87		dBc
HD2		2V_PP, 20 MHz⁽⁷⁾ (SOT-23)			−79		dBc
HD2		2V_PP, 20 MHz⁽⁷⁾ (SOIC)			−72		dBc
HD2H		2V_PP, 60 MHz⁽⁷⁾ (SOT-23)			−63		dBc
HD2H		2V_PP, 60 MHz⁽⁷⁾ (SOIC)			−64		dBc
HD3L	3^rd Harmonic distortion	2V_PP, 5 MHz⁽⁷⁾ (SOT-23)			−96		dBc
HD3L		2V_PP, 5 MHz⁽⁷⁾ (SOIC)			−98		dBc
HD3		2V_PP, 20 MHz⁽⁷⁾ (SOT-23)			−88		dBc
HD3		2V_PP, 20 MHz⁽⁷⁾ (SOIC)			−82		dBc
HD3H		2V_PP, 60 MHz⁽⁷⁾ (SOT-23)			−70		dBc
HD3H		2V_PP, 60 MHz⁽⁷⁾ (SOIC)			−65		dBc
OIM3	IMD	75 MHz, P_O = 10dBm/ tone			−67		dBc
V_N	Input referred voltage noise	>1 MHz			1.83		nV/√Hz
I_N	Input referred inverting noise current	>1 MHz			18.5		pA/√Hz
I_NN	Input referred non-inverting noise current	>1 MHz			3.0		pA/√Hz
SNF	Total input noise floor	>1 MHz			−158		dBm_1Hz
INV	Total integrated input noise	1 MHz to 150 MHz			35		µV
STATIC, DC PERFORMANCE
V_IO	Input offset voltage				±1.0	±4.5	mV
V_IO	Input offset voltage		-40 ≤ T_J ≤ 85			±6.0	mV
DV_IO	Input offset voltage average drift	See⁽⁶⁾			−13		µV/°C
I_BN	Input bias current	Non-Inverting⁽⁵⁾			−6	–15	µA
I_BN	Input bias current	Non-Inverting⁽⁵⁾	-40 ≤ T_J ≤ 85			–21	µA
DI_BN	Input bias current average drift	Non-Inverting⁽⁶⁾			+40		nA/°C
I_BI	Input bias current	Inverting⁽⁵⁾			−8	±30	µA
I_BI	Input bias current	Inverting⁽⁵⁾	-40 ≤ T_J ≤ 85			±34	µA
DI_BI	Input bias current average drift	Inverting⁽⁶⁾			−10		nA/°C
PSRR	Power supply rejection ratio	DC		47	52		dB
PSRR	Power supply rejection ratio	DC	-40 ≤ T_J ≤ 85	45			dB
CMRR	Common mode rejection ration	DC		45	48		dB
CMRR	Common mode rejection ration	DC	-40 ≤ T_J ≤ 85	44			dB
I_CC	Supply current	R_L = ∞		11.0	12.5	16.1	mA
I_CC	Supply current	R_L = ∞	-40 ≤ T_J ≤ 85	10.0		17.5	mA
MISCELLANEOUS PERFORMANCE
R_IN	Input resistance	Non-Inverting			1.4		MΩ
C_IN	Input capacitance	Non-Inverting			1.6		pF
R_OUT	Output resistance	Closed Loop			30		mΩ
V_OL	Output voltage range	R_L = 100 Ω		±3.3	±3.5		V
V_OL	Output voltage range	R_L = 100 Ω	-40 ≤ T_J ≤ 85	±3.2			V
CMIR	Input voltage range	Common Mode		±1.9	±2.2		V
I_O	Output current			50	80		mA

(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that T_J = T_A. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where T_J > T_A. Min/Max ratings are based on production testing unless otherwise specified.

(2) Slew Rate is the average of the rising and falling edges.

(3) All limits are ensured by testing or statistical analysis.

(4) Typical numbers are the most likely parametric norm.

(5) Negative input current implies current flowing out of the device.

(6) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.

(7) Harmonic distortion is strongly influenced by package type (SOT-23 or SOIC). See Application Note section under Harmonic Distortion for more information.

6.6 Typical Characteristics

T_A = 25°C, V_S = ±5 V, R_L = 100 Ω, R_f = 237 Ω (unless otherwise noted)

V₀ = 2 Vpp	R_L = 100 Ω	R_F = 237 Ω

Figure 1. Non-Inverting Frequency Response

V_OUT = 0.5 V_PP	A_V = 2	R_F = 232 Ω

Figure 3. Small Signal Bandwidth

A_V = 4	V_O = 2 V_PP	R_F = 237 Ω

Figure 5. Frequency Response for Various R_Ls, A_V = 4

A_V = 2	V_OUT = 6 V_PP	R_L = 100 Ω

Figure 7. Step Response, 6 V_PP

2 V_PP	A_V = 2	R_F = 237 Ω

Figure 9. Harmonic Distortion vs Load and Frequency
(SOIC Package)

A_V = -1	R_L = 1 kΩ

Figure 11. R_S and Settling Time vs C_L

A_V = 2	R_F = 237 Ω	R_L = 100 Ω

Figure 13. HD3 vs Output Power (Across 100 Ω)
(SOIC Package)

Figure 15. Inverting Input Bias
for 3 Representative Units

Figure 17. Noise

V_S = ±5 V	R_L = 100 Ω

Figure 19. Transimpedance

R_F = 237 Ω	R_L = 150 Ω

Figure 21. DG/DP (PAL)

V_OUT = 2 V_PP	R_F = 237 Ω	R_L = 100 Ω

Figure 2. Inverting Frequency Response

A_V = 2	V_O = 2 V_PP	R_F = 237 Ω

Figure 4. Frequency Response for Various R_Ls, A_V = 2

V_O = 2 V_PP	R_L = 100 Ω

Figure 6. Step Response, 2 V_PP

R_L = 100 Ω

Figure 8. Percent Settling vs Time

A_V = 2	R_L = 100 Ω	R_F = 237 Ω

Figure 10. 2 Tone 3rd Order Spurious Level
(SOIC Package)

A_V = 2	R_F = 237 Ω	R_L = 100 Ω

Figure 12. HD2 vs Output Power (Across 100 Ω)
(SOIC Package)

Figure 14. Input Offset for 3 Representative Units

Figure 16. Non-Inverting Input Bias for 3 Representative Units

V_S = ±5 V	R_L = 100 Ω

Figure 18. CMRR, PSRR, R_OUT

R_F = 237 Ω	R_L = 150 Ω

Figure 20. DG/DP (NTSC)