ZHCSW86F July   2005  – August 2024 LMH6702QML-SP

PRODUCTION DATA  

  1.   1
  2. 1特性
  3. 2应用
  4. 3说明
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Quality Conformance Inspection
    4. 5.4 Electrical Characteristics: DC Parameters
    5. 5.5 Electrical Characteristics: AC Parameters
    6. 5.6 Electrical Characteristics: Drift Values Parameters
    7. 5.7 Typical Characteristics
  7. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Feedback Resistor
      2. 6.1.2 Harmonic Distortion
      3. 6.1.3 Capacitive Load Drive
      4. 6.1.4 DC Accuracy and Noise
    2. 6.2 Layout
      1. 6.2.1 Layout Guidelines
  8. 7Device and Documentation Support
    1. 7.1 接收文档更新通知
    2. 7.2 支持资源
    3. 7.3 Trademarks
    4. 7.4 静电放电警告
    5. 7.5 术语表
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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Harmonic Distortion

The LMH6702 has been optimized for exceptionally low harmonic distortion while driving very demanding resistive or capacitive loads. Generally, when used as the input amplifier to very high-speed flash ADCs, the distortions introduced by the converter dominate over the low LMH6702 distortions. Capacitor CSS, shown across the supplies in Figure 6-1 and Figure 6-2, is critical to achieving the lowest 2nd harmonic distortion. For absolute minimum distortion levels, keep the supply decoupling currents (ground connections to CPOS, and CNEG in Figure 6-1 and Figure 6-2) separate from the ground connections to sensitive input circuitry (such as RG, RT, and RIN ground connections). Splitting the ground plane in this manner, and separately routing the high frequency current spikes on the decoupling caps back to the power supply (similar to a star connection layout technique) provides minimum coupling back to the input circuitry and results in best harmonic distortion response (especially 2nd-order distortion).

If this layout technique has not been observed on a particular application board, the supply decoupling capacitors can adversely affect HD2 performance by increasing the coupling phenomenon already mentioned. Figure 6-3 shows actual HD2 data on a board where the ground plane is shared between the supply decoupling capacitors and the rest of the circuit. After these capacitors are removed, the HD2 distortion levels reduce significantly, especially between 10MHz to 20MHz, as shown in Figure 6-3.

LMH6702QML-SP Decoupling Current Adverse Effect on a Board
                    With Shared Ground PlaneFigure 6-3 Decoupling Current Adverse Effect on a Board With Shared Ground Plane

At these extremely low distortion levels, the high-frequency behavior of decoupling capacitors themselves can be significant. In general, lower-value decoupling capacitors tend to have higher resonance frequencies, making lower-value decoupling capacitors more effective for higher-frequency regions. A particular application board that has been laid out correctly with ground returns split to minimize coupling benefits the most by having low-value and higher-value capacitors paralleled to take advantage of the effective bandwidth of each, and extend the low-distortion frequency range.