6 Pin Configuration and Functions

Figure 6-1 RHS Package48-Pin WQFNTop View

Table 6-1 Pin Functions⁽³⁾

PIN		TYPE	DESCRIPTION
NAME	NO.	TYPE	DESCRIPTION
CLKin_SEL0	19	I	Clock input selection pins ⁽²⁾
CLKin_SEL1	22	I	Clock input selection pins ⁽²⁾
CLKin0	20	I	Universal clock input 0 (differential or single-ended)
CLKin0*	21	I	Universal clock input 0 (differential or single-ended)
CLKin1	40	I	Universal clock input 1 (differential or single-ended)
CLKin1*	40	I	Universal clock input 1 (differential or single-ended)
CLKoutA_TYPE0	14	I	Bank A output buffer type selection pins ⁽²⁾
CLKoutA_TYPE1	47	I	Bank A output buffer type selection pins ⁽²⁾
CLKoutB_TYPE0	23	I	Bank B output buffer type selection pins ⁽²⁾
CLKoutB_TYPE1	39	I	Bank B output buffer type selection pins ⁽²⁾
CLKoutA0	1	O	Differential clock output A0. Output type set by CLKoutA_TYPE pins.
CLKoutA0*	2	O
CLKoutA1	3	O	Differential clock output A1. Output type set by CLKoutA_TYPE pins.
CLKoutA1*	4	O
CLKoutA2	6	O	Differential clock output A2. Output type set by CLKoutA_TYPE pins.
CLKoutA2*	7	O
CLKoutA3	9	O	Differential clock output A3. Output type set by CLKoutA_TYPE pins.
CLKoutA3*	10	O
CLKoutA4	11	O	Differential clock output A4. Output type set by CLKoutA_TYPE pins.
CLKoutA4*	12	O
CLKoutB4*	25	O	Differential clock output B4. Output type set by CLKoutB_TYPE pins.
CLKoutB4	26	O
CLKoutB3*	27	O	Differential clock output B3. Output type set by CLKoutB_TYPE pins.
CLKoutB3	28	O
CLKoutB2*	30	O	Differential clock output B2. Output type set by CLKoutB_TYPE pins.
CLKoutB2	31	O
CLKoutB1*	33	O	Differential clock output B1. Output type set by CLKoutB_TYPE pins.
CLKoutB1	34	O
CLKoutB0*	35	O	Differential clock output B0. Output type set by CLKoutB_TYPE pins.
CLKoutB0	36	O
DAP	DAP	GND	Die Attach Pad. Connect to the PCB ground plane for heat dissipation.
GND	13, 18, 24, 37, 43, 48	GND	Ground
NC	38	—	Not connected internally. Pin may be floated, grounded, or otherwise tied to any potential within the Supply Voltage range stated in Absolute Maximum Ratings.
OSCin	16	I	Input for crystal. Can also be driven by a XO, TCXO, or other external single-ended clock.
OSCout	17	O	Output for crystal. Leave OSCout floating if OSCin is driven by a single-ended clock.
REFout	44	O	LVCMOS reference output. Enable output by pulling REFout_EN pin high.
REFout_EN	46	I	REFout enable input. Enable signal is internally synchronized to selected clock input. ⁽²⁾
V_CC	15, 42	PWR	Power supply for Core and Input Buffer blocks. The Vcc supply operates from 3.3 V. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcc pin.
V_CCOA	5, 8	PWR	Power supply for Bank A Output buffers. V_CCOA can operate from 3.3 V or 2.5 V. The V_CCOA pins are internally tied together. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcco pin. ⁽¹⁾
V_CCOB	29, 32	PWR	Power supply for Bank B Output buffers. V_CCOB can operate from 3.3 V or 2.5 V. The V_CCOB pins are internally tied together. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcco pin. ⁽¹⁾
V_CCOC	45	PWR	Power supply for REFout Output buffer. V_CCOC can operate from 3.3 V or 2.5 V. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcco pin. ⁽¹⁾

(1) The output supply voltages or pins (V_CCOA, V_CCOB, and V_CCOC) will be called V_CCO in general when no distinction is needed, or when the output supply can be inferred from the output bank/type.

(2) CMOS control input with internal pull-down resistor.

(3) Any unused output pin should be left floating with minimum copper length (see note in Clock Outputs), or properly terminated if connected to a transmission line, disabled, or set to Hi-Z, if possible. See Clock Outputs for output configuration and Termination and Use of Clock Drivers for output interface and termination techniques.