In practical system applications, power supply noise (ripple) can be generated from switching power supplies, digital ASICs or FPGAs, and so on. While power supply bypassing will help filter out some of this noise, it is important to understand the effect of power supply ripple on the device performance. When a single-tone sinusoidal signal is applied to the power supply of a clock distribution device, such as LMK00338, it can produce narrow-band phase modulation as well as amplitude modulation on the clock output (carrier). In the single-side band phase noise spectrum, the ripple-induced phase modulation appears as a phase spur level relative to the carrier (measured in dBc).

For the LMK00338, power supply ripple rejection, or PSRR, was measured as the single-sideband phase spur level (in dBc) modulated onto the clock output when a ripple signal was injected onto the V_CCO supply. The PSRR test setup is shown in Figure 9-1.

Figure 9-1 PSRR Test Setup

A signal generator was used to inject a sinusoidal signal onto the V_CCO supply of the DUT board, and the peak-to-peak ripple amplitude was measured at the V_CCO pins of the device. A limiting amplifier was used to remove amplitude modulation on the differential output clock and convert it to a single-ended signal for the phase noise analyzer. The phase spur level measurements were taken for clock frequencies of 156.25 MHz and 312.5 MHz under the following power supply ripple conditions:

• Ripple amplitude: 100 mVpp on V_CCO = 2.5 V
• Ripple frequencies: 100 kHz, 1 MHz, and 10 MHz

Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as follows:

The PSRR vs. Ripple Frequency plots in Section 6.6 show the ripple-induced phase spur levels at 156.25 MHz and 312.5 MHz. The LMK00338 exhibits very good and well-behaved PSRR characteristics across the ripple frequency range. The phase spur levels for HCSL are below –72 dBc at 156.25 MHz and below –63 dBc at 312.5 MHz. Using Equation 10, these phase spur levels translate to Deterministic Jitter values of 1.02 ps pk-pk at 156.25 MHz and 1.44 ps pk-pk at 312.5 MHz. Testing has shown that the PSRR performance of the device improves for V_CCO = 3.3 V under the same ripple amplitude and frequency conditions.