4 Revision History
Changes from Revision B (June 2017) to Revision C (July 2021)
- 将数据表标题从LMK00338 8 路输出差动时钟缓冲器和电平转换器 更改为：LMK00338 8 路输出 PCIe 第 1 代/第 2 代/第 3 代/第 4 代/第 5 代时钟缓冲器和电平转换器
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- 更改了目标应用，方法为将附加应用添加到第二个和第三个要点，并且从第一个要点中删除高速和串行接口。Go
- 在数据表中添加了 PCIe 第 5 代Go
- Changed guarantee to ensure throughout.Go
- Added PCIe 4.0 compliance dataGo
- Added additive RMS phase jitter for PCIe 4.0 and PCIe 5.0 to the Electrical
Characteristics tableGo
- Removed the LVPECL Phase Noise at 100 MHz graph Go
- Changed the third paragraph in Driving the Clock Inputs section to include CLKin* and LVCMOS text. Revised to better correspond with information in the Electrical Characteristics tableGo
- Changed the bypass cap text to signal attenuation text of the fourth paragraph in Driving the Clock Inputs section.Go
- Changed the Single-Ended LVCMOS Input, DC Coupling with Common Mode Biasing image with revised graphic.Go
Changes from Revision A (October 2014) to Revision B (June 2017)
- 已将整个数据表中的 CLKoutA_EN 和 CLKoutB_EN 引脚更改为 CLKoutA_EN 和 CLKoutB_EN
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Changes from Revision * (December 2013) to Revision A (October 2014)
- 添加、更新或重命名了以下各个部分：器件信息表、应用和实施；电源建议；布局；器件和文档支持；机械、封装和可订购信息
Go
- Added PCIE Gen4 additive jitter to the Electrical Characteristics table Go
- Changed 1 MHz to 12 kHz Go
- Added Figure 10-1
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