米6体育平台手机版

8.1 Pin Characteristics

		TYP	UNIT
C_IN	Input Capacitance	1	pF
R_PU	Input Pullup Resistance	51	kΩ
R_PD	Input Pulldown Resistance	51	kΩ
C_PD	Power Dissipation Capacitance (per output)	2	pF
R_OUT	Output impedance	7	Ω

8.2 Absolute Maximum Ratings⁽¹⁾⁽²⁾

Over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
VDD	Core Supply Voltage	–0.3	3.6	V
VDDO	Output Supply Voltage	–0.3	3.6	V
V_IN	Input Voltage Range	–0.3	VDD +0.3	V
T_J	Junction Temperature		150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.

8.3 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage temperature range		–65	150	°C
V_(ESD)	Electrostatic discharge⁽³⁾	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾		1000	V
V_(ESD)	Electrostatic discharge⁽³⁾	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾		250	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(3) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in to the device.

8.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

		MIN	TYP	MAX	UNIT
VDD	Core Supply Voltage	3.135	3.3	3.465	V
VDDO	Output Supply Voltage	3.135	3.3	3.465	V
		2.375	2.5	2.625
		1.65	1.8	1.95
		1.425	1.5	1.575
T_A	Ambient Temperature	-40		85	°C
T_J	Junction Temperature			125	°C

8.5 Thermal Information

Over operating free-air temperature range (unless otherwise noted)

	THERMAL METRIC⁽¹⁾		MIN	TYP	MAX	UNIT
R _θJA	Package Thermal Impedance, Junction to Air (0 LFPM)				116	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

8.6 Power Supply Characteristics

Over operating free-air temperature range (unless otherwise noted)

	PARAMETER			MIN	TYP	MAX	UNIT
IDD	Power Supply Current through VDD					21	mA
IDDO	Power Supply Current through VDDO					5	mA

8.7 LVCMOS / LVTTL DC Characteristics

Over operating free-air temperature range (unless otherwise noted)

	PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
V_IH	Input High Voltage	CLK_EN, CLK_SEL, OE		2	VDD + 0.3	V
V_IH	Input High Voltage	LVCMOS_CLK		2	VDD + 0.3	V
V_IL	Input Low Voltage	CLK_EN, CLK_SEL, OE		–0.3	0.8	V
V_IL	Input Low Voltage	LVCMOS_CLK		–0.3	1.3	V
I_IH	Input High Current	CLK_EN, CLK_SEL, OE	VDD = 3.465 V, V_IN = 3.465 V		5	µA
I_IH	Input High Current	LVCMOS_CLK	VDD = 3.465 V, V_IN = 3.465 V		150	µA
I_IL	Input Low Current	CLK_EN, CLK_SEL, OE	VDD = 3.465 V, V_IN = 0 V	–150		µA
I_IL	Input Low Current	LVCMOS_CLK	VDD = 3.465 V, V_IN= 0 V	–5		µA
V_OH	Output High Voltage⁽¹⁾		VDDO = 3.3 V ± 5%	2.6		V
			VDDO = 2.5 V ± 5%	1.8
			VDDO = 1.8 V ± 0.15 V	1.5
			VDDO = 1.5 V ± 5%	VDDO – 0.3
V_OL	Output Low Voltage⁽¹⁾		VDDO = 3.3 V ± 5%		0.5	V
			VDDO = 2.5 V ± 5%		0.5
			VDDO = 1.8 V ± 0.15 V		0.4
			VDDO = 1.5 V ± 5%		0.35
I_OZL	Output Hi-Z Current Low			–5		µA
I_OZH	Output Hi-Z Current High				5	µA

(1) Outputs terminated with 50 Ω to VDDO/2.

8.8 Differential Input DC Characteristics

Over operating free-air temperature range (unless otherwise noted)

	PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
V_ID	Differential Input Voltage Swing, (V_IH-V_IL)⁽¹⁾			0.15	1.3	V
V_ICM	Input Common Mode Voltage⁽¹⁾⁽²⁾			0.5	VDD – 0.85	V
I_IH	Input High Current⁽³⁾	nCLK	VDD = 3.465 V, V_IN = 3.465 V		150	µA
I_IH	Input High Current⁽³⁾	CLK	VDD = 3.465 V, V_IN = 3.465 V		150	µA
I_IL	Input Low Current⁽³⁾	nCLK	VDD = 3.465 V , V_IN = 0 V	-150		µA
I_IL	Input Low Current⁽³⁾	CLK	VDD = 3.465 V, V_IN = 0 V	-5		µA

(1) V_IL should not be less than -0.3 V.

(2) Input common mode voltage is defined as V_IH.

(3) For I_IH and I_IL measurements on CLK or nCLK, one must comply with V_ID and V_ICM specifications by using the appropriate bias on nCLK or CLK.

8.9 Electrical Characteristics (VDDO = 3.3 V ± 5%)

Over recommended operating free-air temperature range (unless otherwise noted), VDD = VDDO = 3.3V ± 5%,
All AC parameters measured at ≤ 350 MHz unless otherwise noted.

	PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_OUT	Maximum Output Frequency⁽¹¹⁾⁽¹⁾					350	MHz
t_PDLH	Propagation Delay, Low to High⁽⁹⁾	LVCMOS_CLK⁽²⁾, CLK/nCLK⁽³⁾	0°C to 70°C	1.1		2.1	ns
t_PDLH	Propagation Delay, Low to High⁽⁹⁾	LVCMOS_CLK⁽²⁾, CLK/nCLK⁽³⁾	–40°C to 85°C	0.95		2.2	ns
t_SK(O)	Output Skew⁽¹⁾⁽⁴⁾⁽⁵⁾		Measured on rising edge			35	ps
t_SK(PP)	Part-to-Part Skew⁽⁹⁾⁽⁵⁾⁽⁶⁾					700	ps
t_R/t_F	Output Rise/Fall Time⁽⁹⁾		20% to 80%	50		700	ps
J_ADD	Additive Jitter⁽⁷⁾		f=125 MHz, Input slew rate ≥ 3 V/ns, 12 kHz to 20 MHz integration band		0.04		ps RMS
PN_FLOOR	Phase Noise Floor⁽⁸⁾		f = 125 MHz, Input slew rate ≥ 3 V/ns				dBc/Hz
			10 kHz offset		-155
			100 kHz offset		-162
			1 MHz offset		-166
			10 MHz offset		-166
			20 MHz offset		-166
ODC	Output Duty Cycle⁽⁹⁾⁽¹⁰⁾		REF = CLK/nCLK	45%		55%
ODC	Output Duty Cycle⁽⁹⁾⁽¹⁰⁾		REF = LVCMOS_CLK, f ≤ 300 MHz	45%		55%
t_EN	Output Enable Time				5		ns
t_DIS	Output Disable Time				5		ns

(1) These AC parameters are specified by characterization. Not tested in production.

(2) Measured from the VDD/2 of the input to the VDDO/2 of the output.

(3) Measured from the differential input crossing point to VDDO/2 of the output.

(4) Defined as skew between outputs at the same supply voltage and with equal loading conditions. Measured at VDDO/2 of the output.

(5) Parameter is defined in accordance with JEDEC Standard 65.

(6) Calculation for part-to-part skew is the difference between the fastest and slowest t_PD across multiple devices, operating at the same supply voltage, same frequency, same temperature, with equal load conditions, and using the same type of inputs on each device.

(7) Buffer Additive Jitter: J_ADD = SQRT(J_SYSTEM² - J_SOURCE²), where J_SYSTEM is the RMS jitter of the system output (source+buffer) and J_SOURCE is the RMS jitter of the input source, and system output noise is not correlated to the input source noise. Additive jitter should be considered only when the input source noise floor is 3 dB or better than the buffer noise floor (PN_FLOOR). This is usually the case for high-quality ultra-low-noise oscillators. Please refer to System-Level Phase Noise and Additive Jitter Measurement for input source and measurement details.

(8) Buffer Phase Noise Floor: PN_FLOOR (dBc/Hz) = 10 x log10[10^(PN_SYSTEM/10) – 10^(PN_SOURCE/10)], where PN_SYSTEM is the phase noise floor of the system output (source+buffer) and PN_SOURCE is the phase noise floor of the input source. Buffer Phase Noise Floor should be considered only when the input source noise floor is 3 dB or better than the buffer noise floor (PN_FLOOR). This is usually the case for high-quality ultra-low-noise oscillators. Please refer to System-Level Phase Noise and Additive Jitter Measurement for input source and measurement details.

(9) These AC parameters are specified by design. Not tested in production

(10) 50% Input duty cycle

(11) There is no minimum input / output frequency provided the input slew rate is sufficiently fast. Refer to Input Slew Rate Considerations.

8.10 Electrical Characteristics (VDDO = 2.5 V ± 5%)

Over recommended operating free-air temperature range (unless otherwise noted), VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%,
All AC parameters measured at ≤ 350 MHz unless otherwise noted.

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_OUT	Maximum Output Frequency⁽¹⁰⁾⁽¹⁾					350	MHz
t_PDLH	Propagation Delay, Low to High⁽⁸⁾	LVCMOS_CLK⁽²⁾, CLK/nCLK⁽³⁾	0°C to 70°C	1.1		2.1	ns
t_PDLH	Propagation Delay, Low to High⁽⁸⁾	LVCMOS_CLK⁽²⁾, CLK/nCLK⁽³⁾	–40°C to 85°C	0.95		2.2	ns
t_SK(O)	Output Skew⁽¹⁾⁽⁴⁾⁽⁵⁾		Measured on rising edge			35	ps
t_SK(PP)	Part-to-Part Skew⁽⁸⁾⁽⁵⁾⁽⁶⁾					700	ps
t_R/t_F	Output Rise/Fall Time⁽⁸⁾		20% to 80%	50		700	ps
J_ADD	Additive Jitter⁽⁷⁾		f=125 MHz, Input slew rate ≥ 3 V/ns, 12 kHz to 20 MHz integration band		0.04		ps RMS
ODC	Output Duty Cycle⁽⁸⁾⁽⁹⁾		REF = CLK/nCLK	45%		55%
ODC	Output Duty Cycle⁽⁸⁾⁽⁹⁾		REF = LVCMOS_CLK, f ≤ 300 MHz	45%		55%
t_EN	Output Enable Time				5		ns
t_DIS	Output Disable Time				5		ns

(1) These AC parameters are specified by characterization. Not tested in production.

(2) Measured from the VDD/2 of the input to the VDDO/2 of the output.

(3) Measured from the differential input crossing point to VDDO/2 of the output.

(4) Defined as skew between outputs at the same supply voltage and with equal loading conditions. Measured at VDDO/2 of the output.

(5) Parameter is defined in accordance with JEDEC Standard 65.

(6) Calculation for part-to-part skew is the difference between the fastest and slowest t_PD across multiple devices, operating at the same supply voltage, same frequency, same temperature, with equal load conditions, and using the same type of inputs on each device.

(7) Buffer Additive Jitter: J_ADD = SQRT(J_SYSTEM² - J_SOURCE²), where J_SYSTEM is the RMS jitter of the system output (source+buffer) and J_SOURCE is the RMS jitter of the input source, and system output noise is not correlated to the input source noise. Additive jitter should be considered only when the input source noise floor is 3 dB or better than the buffer noise floor (PN_FLOOR). This is usually the case for high-quality ultra-low-noise oscillators. Please refer to System-Level Phase Noise and Additive Jitter Measurement for input source and measurement details.

(8) These AC parameters are specified by design. Not tested in production.

(9) 50% Input Duty Cycle

(10) There is no minimum input / output frequency provided the input slew rate is sufficiently fast. Refer to Input Slew Rate Considerations.

8.11 Electrical Characteristics (VDDO = 1.8 V ± 0.15 V)

Over recommended operating free-air temperature range (unless otherwise noted), VDD = 3.3 V ± 5%,
VDDO = 1.8 V ± 0.15 V. All AC parameters measured at ≤ 350 MHz unless otherwise noted.

	PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_OUT	Maximum Output Frequency⁽¹⁰⁾⁽¹⁾					350	MHz
t_PDLH	Propagation Delay, Low to High⁽⁸⁾	LVCMOS_CLK⁽²⁾, CLK/nCLK⁽³⁾	0°C to 70°C	1.1		2.2	ns
t_PDLH	Propagation Delay, Low to High⁽⁸⁾	LVCMOS_CLK⁽²⁾, CLK/nCLK⁽³⁾	–40°C to 85°C	0.95		2.3	ns
t_SK(O)	Output Skew⁽¹⁾⁽⁴⁾⁽⁵⁾		Measured on rising edge			35	ps
t_SK(PP)	Part-to-Part Skew⁽⁸⁾⁽⁵⁾⁽⁶⁾					700	ps
t_R/t_F	Output Rise/Fall Time⁽⁸⁾		20% to 80%	100		700	ps
J_ADD	Additive Jitter⁽⁷⁾		f=125 MHz, Input slew rate ≥ 3 V/ns, 12 kHz to 20 MHz integration band		0.04		ps RMS
ODC	Output Duty Cycle⁽⁸⁾⁽⁹⁾		REF = CLK/nCLK	45%		55%
ODC	Output Duty Cycle⁽⁸⁾⁽⁹⁾		REF = LVCMOS_CLK, f ≤ 300 MHz	45%		55%
t_EN	Output Enable Time				5		ns
t_DIS	Output Disable Time				5		ns