ZHCS747D January 2012 – September 2021 LMK01801
PRODUCTION DATA
CLKout12_13_DDLY and CLKout12_13_HS sets the digital delay used for CLKout12 and CLKout13. CLKout12_13_DDLY only takes effect during a SYNC event and if the NO_SYNC_CLKout12_13 bit is cleared for this clock group.
Programming CLKout12_13_DDLY can require special attention. See section Section 9.4.6.1 for more details.
Using a CLKout12_13_DDLY value of 13 or greater will cause the clock outputs to operate in extended mode regardless of the clock group’s divide value or the half step value.
One clock cycle is equal to the period of the clock distribution path. The period of the clock distribution path is equal to clock divider value divided by the CLKin1 frequency.
| R4[13:4] | Delay (Divide = 1) | Delay (Divide >1) | Power Mode |
|---|---|---|---|
| 0 (0x00) | 5 clock cycles | 6 clock cycles | Normal Mode |
| 1 (0x01) | 5 clock cycles | 6 clock cycles | |
| 2 (0x02) | 5 clock cycles | 6 clock cycles | |
| 3 (0x03) | 5 clock cycles | 6 clock cycles | |
| 4 (0x04) | 5 clock cycles | 6 clock cycles | |
| 5 (0x05) | 5 clock cycles | 6 clock cycles | |
| 6 (0x06) | 6 clock cycles | 7 clock cycles | |
| 7 (0x07) | 7 clock cycles | 8 clock cycles | |
| ... | ... | ... | |
| 12 (0x0C) | 12 clock cycles | 13 clock cycles | |
| 13 (0x0D) | 13 clock cycles | 14 clock cycles | Extended Mode |
| ... | ... | ... | |
| 520 (0x208) | 520 clock cycles | 521 clock cycles | |
| 521 (0x209) | 521 clock cycles | 522 clock cycles | |
| 522 (0x20A) | 522 clock cycles | 523 clock cycles |