This section discusses Fixed Digital Delay and associated registers.

Clock outputs 0 to 11 may be delayed after synchronization by a fixed offset of 5 clock distribution path cycles. The CLKoutX_Y_OFFSET_PD register bit inserts the delay for each respective clock group. By default, the fixed offset is enabled for CLKout8_11 and disabled for CLKout0_3 and CLKout4_7. CLKoutX_Y_OFFSET_PD aligns the specified clock group with CLKout12_13 after a SYNC event upon meeting the following conditions:

1. The input clock frequency of the specified clock group(s) is the same as CLKout12_13 (CLKin1).
2. CLKout12_13 does not have any digital or analog delays enabled.

See SYNC Timing for further synchronization details on CLKoutX_Y_OFFSET_PD.

Clock outputs 12 and 13 may be delayed relative to CLKout8 to CLKout11 by up to 517.5 clock distribution path periods if divide is 1 and 518.5 clock distribution path periods if divide is greater than 1. By programming a digital delay value from 4.5 to 522 clock distribution path periods, a relative clock output delay from 0 to 517.5 periods is achieved. The CLKout12_13_DDLY register sets the digital delay as shown in the table Table 9-2.

The CLKout12_13_DDLY value only takes effect during a SYNC event and if the NO_SYNC_CLKout12_13 bit is cleared for this clock group. See Section 9.4.6 for more information.

The resolution of digital delay is related to the frequency at the input to the Clock Group 4 (CG4) clock distribution path.

Digital Delay Resolution = 1 / (2 * Clock Frequency)

The digital delay between clock outputs can be dynamically adjusted with minimum or no disruption of the output clocks. See Section 9.4.6.1 for more information.