11.2.3.1 Fine Frequency Margining

IEEE802.3 dictates that Ethernet frames stay compliant to the standard specifications when clocked with a reference clock that is within ±100 ppm of its nominal frequency. In the worst case, an RX node with its local reference clock at –100 ppm from its nominal frequency should be able to work seamlessly with a TX node that has its own local reference clock at +100 ppm from its nominal frequency. Without any clock compensation on the RX node, the read pointer will severely lag behind the write pointer and cause FIFO overflow errors. On the contrary, when the RX node’s local clock operates at 100 ppm from its nominal frequency and the TX node’s local clock operates at –100 ppm from its nominal frequency, FIFO underflow errors occur without any clock compensation.

To prevent such overflow and underflow errors from occuring, modern ASICs and FGPAs include a clock compensation scheme that introduces elastic buffers. Such a system, shown in Figure 80, is validated thoroughly during the validation phase by interfacing slower nodes with faster ones and ensuring compliance to IEEE802.3. The LMK03318 provides the ability to fine tune the frequency of its outputs based on changing its on-chip load capacitance when operated with a crystal input. This fine tuning can be done through I2C or through the GPIO5 pin as described inCrystal Input Interface (SEC_REF). A total of ±50 ppm frequency tuning is achievable when using pullable crystals whose C0/C1 ratio is less than 250. The change in load capacitance is implemented in a manner such that the outputs of the LMK03318 undergo a smooth monotic change in frequency.

Figure 81. System Implementation with Clock Compensation for Standards Compliance