11.2.4 Design Requirements

Consider a typical wired communications application, like a top-of-rack switch, which needs to clock high data rate 10 Gbps or 100 Gbps Ethernet PHYs and other macros like PCI Express, Fast Ethernet and CPLD. For such asynchronous systems, the reference input can be a crystal. In such systems, the clocks are expected to be available upon powerup without the need for any device-level programming. An example of the clock input and output requirements is :

• Clock Input:
  • 25-MHz crystal
• Clock Outputs:
  • 2x 156.25-MHz clock for uplink 10.3125 Gbps, LVPECL
  • 2x 125-MHz clock for downlink 3.125 Gbps, LVPECL
  • 2x 100-MHz clock for PCI Express, HCSL
  • 1x 25-MHz clock for Fast Ethernet, LVDS
  • 2x 33.3333-MHz clock for CPLD, 1.8-V LVCMOS

The section below describes the detailed design procedure to generate the required output frequencies for the above scenario using LMK03318.