12.4.7 Slow Reference Input Clock Startup

If the reference input clock is direct coupled to the LMK03318 and has a very slow startup time of over 10 ms, as defined from the time power supply reaches acceptable operating voltage for the reference input generator, which is typically 2.97 V for a 3.3-V supply, to the time when the reference input has a stable clock output, take additional care to prevent unsuccessful PLL calibration. In the case of the reference input building up its amplitude slowly, TI recommends setting the input buffer to differential irrespective of the input type (LVCMOS or differential). In case of LVCMOS inputs, TI also recommends enabling on-chip termination by setting R29.4 (for primary input) and/or R29.5 (for secondary input) to 1. There is one of two additional steps that need to be taken. The first approach is to add a capacitor to GND on the PDN pin that forms a R-C time constant with the internal 200-kΩ pullup resistor. This R-C time constant can be designed to delay the low-to-high transition of PDN, until after the reference input clock is stable. The second approach is to program a larger PLL closed loop delay in R119[3-2] that is longer than the time taken for the reference input clock to be stable.