10.3.1 Device Block-Level Description

The LMK03318 includes an on-chip fractional PLL with integrated VCO that supports a frequency range of 4.8 GHz to 5.4 GHz. The PLL block consists of an input selection MUX, a phase frequency detector (PFD), charge pump, on-chip passive loop filter that only needs an external capacitor to ground, a feedback divider that can support both integer and fractional values, and a delta-sigma engine for spur suppression in fractional PLL mode. The universal inputs support single-ended and differential clocks in the frequencies of 1 MHz to 300 MHz; the secondary input additionally supports crystals in the frequencies of 10 MHz to 52 MHz. When the PLL operates with the crystal as its reference, the output frequencies can be margined based on changing the on-chip capacitor loading on each leg of the crystal. Completing the device is the combination of integer output dividers and universal output buffers. The PLL is powered by on-chip low dropout (LDO) linear voltage regulators, and the regulated supply network is partitioned such that the sensitive analog supplies are running from separate LDOs than the digital supplies which use their own LDO. The LDOs provide isolation of the isolation of the PLL from any noise in the external power supply rail with a PSNR of better than –70 dBc at 50-kHz to 1-MHz ripple frequencies at 1.8-V output supplies and better than –80 dBc at 50-kHz to 1-MHz ripple frequencies at > 2.5-V output supplies. The regulator capacitor pins must each be connected to ground by 10-µF capacitors to ensure stability.