10.4.10 Loop Filter

The PLL supports programmable loop bandwidth from 200 Hz to 1 MHz. The loop filter components, R2, C1, R3, and C3, can be configured by programming R67, R68, R69, and R70 for the PLL. C2 for the PLL is an external component that is added on the LF pin. When the PLL is configured in the fractional mode, R69.0 should be set to 1 and R118[2-0] should be set to 0x7. When the PLL is configured in integer mode, R69.0 should be set to 0 and R118[2-0] should be set to 0x3 for second-order (NOTE: R69 should be set to 0x0) or 0x7 for third-order, respectively. When the PLL's loop bandwidth is desired to be set to 200 Hz, R120.0 should be set to 0. Figure 58 shows the loop filter structure of the PLL.

It is important to set the PLL to best possible bandwidth to minimize output jitter. A high bandwidth (≥ 100 kHz) provides best input signal tracking and is therefore desired with a clean input reference (clock generator mode). A low bandwidth (≤ 1 kHz) is desired if the input signal quality is unknown (jitter cleaner mode). TI provides the WEBENCH Clock Architect that makes it easy to select the right loop filter components.

Figure 58. Loop Filter Structure of PLL