米6体育平台手机版

ZHCSHU9K September 2011 – December 2023 LMK03806

PRODUCTION DATA

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机械数据 (封装 | 引脚)

NKD|64
- MPQS032B

散热焊盘机械数据 (封装 | 引脚)

NKD|64
- QFND765

订购信息

5.5 Electrical Characteristics

3.15 V ≤ V_CC ≤ 3.45 V, –40°C ≤ T_A ≤ 85°C, Junction Temperature T_J ≤ 125°C.
Typical values represent most likely parametric norms at V_CC = 3.3 V, T_A = 25°C, at Recommended Operating ConditionsRecommended Operating Conditions at the time of product characterization and are not ensured.⁽³⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
CURRENT CONSUMPTION
I_{CC_PD}	Powerdown supply current	No DC path to ground on OSCout1/1*⁽¹⁾		1		mA
I_{CC_CLKS}	Supply current with all clocks enabled⁽²⁾	CLKoutX_Y_DIV = 16, CLKoutX_TYPE = 1 (LVDS), PLL locked		445		mA
EXTERNAL CLOCK (OSCin) SPECIFICATIONS
f_OSCin	PLL reference Input⁽⁴⁾		1		500	MHz
SLEW_OSCin	PLL reference clock minimum slew rate on OSCin⁽⁹⁾	20% to 80%	0.15	0.5		V/ns
V_OSCin	Input voltage for OSCin or OSCin*⁽⁹⁾	AC coupled; Single-ended (Unused pin AC coupled to GND)	0.2		2.4	Vpp
V_IDOSCin	Differential voltage swing	AC coupled, see Figure 6-1	0.2		1.55	\|V\|
V_SSOSCin	Differential voltage swing	AC coupled, see Figure 6-1	0.4		3.1	Vpp
V_OSCin-offset	DC offset voltage between OSCin/OSCin* OSCinX* - OSCinX	Each pin AC coupled		20		mV
f_{doubler_max}	Doubler input frequency⁽⁹⁾	EN_PLL_REF_2X = 1; OSCin Duty Cycle 40% to 60%			155	MHz
CRYSTAL OSCILLATOR MODE SPECIFICATIONS
f_XTAL	Crystal frequency range⁽⁹⁾	R_ESR ≤ 40 Ω C_L ≤ 20 pF	16		20.5	MHz
f_XTAL	Crystal frequency range⁽⁹⁾	R_ESR ≤ 80 Ω C_L ≤ 22 pF	6		16	MHz
P_XTAL	Crystal power dissipation	Vectron VXB1 crystal, 20.48 MHz, R_ESR ≤ 40 Ω C_L ≤ 20 pF		120		µW
C_IN	Input capacitance of the OSCin port	–40°C to +85°C		6		pF
RMS JITTER PERFORMANCE
XO mode⁽¹⁴⁾⁽¹⁵⁾⁽¹⁶⁾	Integration bandwidth 10 kHz to 1 MHz	156.25 MHz, LVDS/LVPECL		81		fs
	Integration bandwidth 10 kHz to 1 MHz	312.5 MHz, LVDS/LVPECL		85		fs
	Integration bandwidth 12 kHz to 20 MHz	100 MHz, LVDS		139		fs
		100 MHz, LVPECL		117		fs
		106.25 MHz, LVDS		145		fs
		106.25 MHz, LVPECL		126		fs
		156.25 MHz, LVDS		111		fs
		156.25 MHz, LVPECL		100		fs
		312.5 MHz, LVDS		108		fs
		312.5 MHz, LVPECL		95		fs
		622.08 MHz, LVDS/LVPECL		141		fs
	Integration bandwidth 637 kHz to 10 MHz	106.25 MHz, LVDS		78		fs
	Integration bandwidth 637 kHz to 10 MHz	106.25 MHz, LVPECL		60		fs
	Integration bandwidth 1.875 MHz to 20 MHz	156.25 MHz, LVDS		70		fs
		156.25 MHz, LVPECL		57		fs
		312.5 MHz, LVDS		57		fs
		312.5 MHz, LVPECL		43		fs
Crystal mode jitter⁽¹⁰⁾⁽¹¹⁾⁽¹²⁾	Integration bandwidth 10 kHz to 1 MHz	156.25 MHz, LVDS/LVPECL		190		fs
	Integration bandwidth 10 kHz to 1 MHz	312.5 MHz, LVDS/LVPECL		200		fs
	Integration bandwidth 12 kHz to 20 MHz	100 MHz, LVDS		235		fs
		100 MHz, LVPECL		210		fs
		106.25 MHz, LVDS		280		fs
		106.25 MHz, LVPECL		250		fs
		156.25 MHz, LVDS		200		fs
		156.25 MHz, LVPECL		195		fs
		312.5 MHz, LVDS		220		fs
		312.5 MHz, LVPECL		190		fs
		622.08 MHz, LVDS/LVPECL		255		fs
	Integration bandwidth 637 kHz to 10 MHz	106.25 MHz, LVDS		90		fs
	Integration bandwidth 637 kHz to 10 MHz	106.25 MHz, LVPECL		65		fs
	Integration bandwidth 1.875 MHz to 20 MHz	156.25 MHz, LVDS		75		fs
		156.25 MHz, LVPECL		65		fs
		312.5 MHz, LVDS		60		fs
		312.5 MHz, LVPECL		45		fs
PHASE NOISE PERFORMANCE
XO mode phase noise	100 MHz (LVDS/LVPECL)⁽¹⁴⁾	10 kHz		–142		dBc/Hz
		100 kHz		–143		dBc/Hz
		1 MHz		–157		dBc/Hz
		10 MHz (LVDS)		–159		dBc/Hz
		20 MHz (LVDS)		–160		dBc/Hz
		10 MHz (LVPECL)		–160		dBc/Hz
		20 MHz (LVPECL)		–161		dBc/Hz
	106.25 MHz (LVDS/LVPECL)⁽¹⁵⁾	10 kHz		–141		dBc/Hz
		100 kHz		–140		dBc/Hz
		1 MHz		–156		dBc/Hz
		10 MHz (LVDS)		–159		dBc/Hz
		20 MHz (LVDS)		–160		dBc/Hz
		10 MHz (LVPECL)		–162		dBc/Hz
		20 MHz (LVPECL)		–163		dBc/Hz
	156.25 MHz (LVDS/LVPECL)⁽¹⁴⁾	10 kHz		–139		dBc/Hz
		100 kHz		–140		dBc/Hz
		1 MHz		–153		dBc/Hz
		10 MHz (LVDS)		–159		dBc/Hz
		20 MHz (LVDS)		–159		dBc/Hz
		10 MHz (LVPECL)		–160		dBc/Hz
		20 MHz (LVPECL)		–160		dBc/Hz
	312.5 MHz (LVDS/LVPECL)⁽¹⁴⁾	10 kHz		–132		dBc/Hz
		100 kHz		–133		dBc/Hz
		1 MHz		–148		dBc/Hz
		10 MHz (LVDS)		–154		dBc/Hz
		20 MHz (LVDS)		–155		dBc/Hz
		10 MHz (LVPECL)		–157		dBc/Hz
		20 MHz (LVPECL)		–158		dBc/Hz
	622.08 MHz (LVDS/LVPECL)⁽¹⁶⁾	10 kHz		–123		dBc/Hz
		100 kHz		–121		dBc/Hz
		1 MHz		–143		dBc/Hz
		10 MHz (LVDS)		–154		dBc/Hz
		20 MHz (LVDS)		–154		dBc/Hz
		10 MHz (LVPECL)		–157		dBc/Hz
		20 MHz (LVPECL)		–158		dBc/Hz
Crystal mode phase noise	100 MHz (LVDS/LVPECL)⁽¹⁰⁾	10 kHz		–129		dBc/Hz
		100 kHz		–137		dBc/Hz
		1 MHz		–156		dBc/Hz
		10 MHz (LVDS)		–158		dBc/Hz
		20 MHz (LVDS)		–159		dBc/Hz
		10 MHz (LVPECL)		–160		dBc/Hz
		20 MHz (LVPECL)		–161		dBc/Hz
	106.25 MHz (LVDS/LVPECL)⁽¹¹⁾	10 kHz		–124		dBc/Hz
		100 kHz		–137		dBc/Hz
		1 MHz		–156		dBc/Hz
		10 MHz (LVDS)		–158		dBc/Hz
		20 MHz (LVDS)		–159		dBc/Hz
		10 MHz (LVPECL)		–160		dBc/Hz
		20 MHz (LVPECL)		–161		dBc/Hz
	156.25 MHz (LVDS/LVPECL)⁽¹⁰⁾	10 kHz		–125		dBc/Hz
		100 kHz		–132		dBc/Hz
		1 MHz		–153		dBc/Hz
		10 MHz (LVDS)		–158		dBc/Hz
		20 MHz (LVDS)		–159		dBc/Hz
		10 MHz (LVPECL)		–160		dBc/Hz
		20 MHz (LVPECL)		–160		dBc/Hz
	312.5 MHz (LVDS/LVPECL)⁽¹⁰⁾	10 kHz		–119		dBc/Hz
		100 kHz		–126		dBc/Hz
		1 MHz		–147		dBc/Hz
		10 MHz (LVDS)		–153		dBc/Hz
		20 MHz (LVDS)		–154		dBc/Hz
		10 MHz (LVPECL)		–156		dBc/Hz
		20 MHz (LVPECL)		–157		dBc/Hz
	622.08 MHz (LVDS/LVPECL)⁽¹²⁾	10 kHz		–110		dBc/Hz
		100 kHz		–120		dBc/Hz
		1 MHz		–140		dBc/Hz
		10 MHz (LVDS)		–153		dBc/Hz
		20 MHz (LVDS)		–153		dBc/Hz
		10 MHz (LVPECL)		–154		dBc/Hz
		20 MHz (LVPECL)		–154		dBc/Hz
PLL PHASE DETECTOR AND CHARGE PUMP SPECIFICATIONS
f_PD	Phase detector frequency				155	MHz
I_CPoutSOURCE	PLL charge pump source current	V_CPout=V_CC/2, PLL_CP_GAIN = 0		100		µA
		V_CPout=V_CC/2, PLL_CP_GAIN = 1		400		µA
		V_CPout=V_CC/2, PLL_CP_GAIN = 2		1600		µA
		V_CPout=V_CC/2, PLL_CP_GAIN = 3		3200		µA
I_CPoutSINK	PLL charge pump sink current	V_CPout=V_CC/2, PLL_CP_GAIN = 0		–100		µA
		V_CPout=V_CC/2, PLL_CP_GAIN = 1		–400		µA
		V_CPout=V_CC/2, PLL_CP_GAIN = 2		–1600		µA
		V_CPout=V_CC/2, PLL_CP_GAIN = 3		–3200		µA
I_CPout%MIS	Charge pump sink/source mismatch	V_CPout=V_CC/2, T_A = 25°C		3%	10%
I_CPoutV_TUNE	Magnitude of charge pump current vs. charge pump voltage variation	0.5 V < V_CPout < V_CC – 0.5 V T_A = 25°C		4%
I_CPout%TEMP	Charge pump current vs. temperature variation			4%
I_CPoutTRI	Charge pump leakage	0.5 V < V_CPout < V_CC – 0.5 V			10	nA
PN10kHz	PLL 1/f noise at 10 kHz offset⁽⁵⁾. Normalized to 1-GHz output frequency	PLL_CP_GAIN = 400 µA		–118		dBc/Hz
PN10kHz		PLL_CP_GAIN = 3200 µA		–121		dBc/Hz
PN1Hz	Normalized phase noise contribution⁽⁶⁾	PLL_CP_GAIN = 400 µA		–222.5		dBc/Hz
PN1Hz	Normalized phase noise contribution⁽⁶⁾	PLL_CP_GAIN = 3200 µA		–227		dBc/Hz
L(f)	PLL phase noise (Assumes a very wide bandwidth, noiseless crystal, 2500-MHz output frequency, and 25-MHz phase detector frequency)	1-kHz Offset		–93		dBc/Hz
		10 kHz		–103		dBc/Hz
		100-kHz Offset		–116		dBc/Hz
		1-MHz Offset		–116		dBc/Hz
INTERNAL VCO SPECIFICATIONS
f_VCO	VCO tuning range		2370		2600	MHz
K_VCO	Fine tuning sensitivity (The range displayed in the typical column indicates the lower sensitivity is typical at the lower end of the tuning range, and the higher tuning sensitivity is typical at the higher end of the tuning range).	f_VCO at low end		16		MHz/V
K_VCO		f_VCO at high end		21		MHz/V
\|ΔT_CL\|	Allowable temperature drift for continuous lock⁽⁷⁾ ⁽⁹⁾	After programming R30 for lock, no changes to output configuration are permitted to guarantee continuous lock			125	°C
L(f)	Phase noise (Assumes a very narrow loop bandwidth)	10-kHz Offset		–87		dBc/Hz
		100-kHz Offset		–112		dBc/Hz
		1-MHz Offset		–133		dBc/Hz
CLOCK SKEW
\|T_SKEW\|	Maximum CLKoutX to CLKoutY⁽⁸⁾ ⁽⁹⁾	LVDS-to-LVDS, T = 25°C, f_CLK = 800 MHz, R_L= 100 Ω AC coupled		30		ps
	Maximum CLKoutX to CLKoutY⁽⁸⁾ ⁽⁹⁾	LVPECL-to-LVPECL, T = 25°C, f_CLK = 800 MHz, R_L= 100 Ω emitter resistors = 240 Ω to GND AC coupled		30		ps
	Maximum skew between any two LVCMOS outputs, same CLKout or different CLKout⁽⁸⁾ ⁽⁹⁾	R_L = 50 Ω, C_L = 5 pF, T = 25°C, F_CLK = 100 MHz.⁽⁸⁾		100		ps
Mixed_SKEW	LVDS or LVPECL to LVCMOS	Same device, T = 25°C, 250 MHz		750		ps
LVDS CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 1
f_CLKout	Operating frequency⁽⁹⁾ ⁽¹³⁾	R_L = 100 Ω			1300	MHz
V_OD	Differential output voltageFigure 6-2	T = 25°C, DC measurement AC-coupled to receiver input R = 100-Ω differential termination	250	400	450	\|mV\|
V_SS	Differential output voltageFigure 6-2		500	800	900	mVpp
ΔV_OD	Change in magnitude of V_OD for complementary output states		–50		50	mV
V_OS	Output offset voltage		1.125	1.25	1.375	V
ΔV_OS	Change in V_OS for complementary output states				35	\|mV\|
T_R / T_F	Output rise time	20% to 80%, R_L = 100 Ω		200		ps
T_R / T_F	Output fall time	80% to 20%, R_L = 100 Ω		200		ps
I_SA I_SB	Output short circuit current - single-ended	Single-ended output shorted to GND, T = 25°C	–24		24	mA
I_SAB	Output short circuit current - differential	Complimentary outputs tied together, T = 25°C	–12		12	mA
LVPECL CLOCK OUTPUTS (CLKoutX)
f_CLKout	Operating frequency⁽⁹⁾ ⁽¹³⁾				1300	MHz
T_R / T_F	20% to 80% output rise	R_L = 100 Ω, emitter resistors = 240 Ω to GND CLKoutX_TYPE = 4 or 5 (1600 or 2000 mVpp)		150		ps
T_R / T_F	80% to 20% output fall time			150		ps
700-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 2
V_OH	Output high voltage	T = 25°C, DC measurement Termination = 50 Ω to V_CC – 1.4 V		V_CC – 1.03		V
V_OL	Output low voltage			V_CC – 1.41		V
V_OD	Output voltageFigure 6-2		305	380	440	\|mV\|
V_SS	Output voltageFigure 6-2		610	760	880	mVpp
1200-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 3
V_OH	Output high voltage	T = 25°C, DC measurement Termination = 50 Ω to V_CC – 1.7 V		V_CC – 1.07		V
V_OL	Output low voltage			V_CC – 1.69		V
V_OD	Output voltageFigure 6-2		545	625	705	\|mV\|
V_SS	Output voltageFigure 6-2		1090	1250	1410	mVpp
1600-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 4
V_OH	Output high voltage	T = 25°C, DC Measurement Termination = 50 Ω to V_CC – 2 V		V_CC – 1.10		V
V_OL	Output low voltage			V_CC – 1.97		V
V_OD	Output voltageFigure 6-2		660	870	965	\|mV\|
V_SS	Output voltageFigure 6-2		1320	1740	1930	mVpp
2000-mVpp LVPECL (2VPECL) CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 5
V_OH	Output high voltage	T = 25°C, DC Measurement Termination = 50 Ω to V_CC – 2.3 V		V_CC – 1.13		V
V_OL	Output low voltage			V_CC – 2.20		V
V_OD	Output voltageFigure 6-2		800	1070	1200	\|mV\|
V_SS	Output voltageFigure 6-2		1600	2140	2400	mVpp
LVCMOS CLOCK OUTPUTS (CLKoutX)
f_CLKout	Operating frequency⁽⁹⁾	5-pF Load			250	MHz
V_OH	Output high voltage	1-mA Load	V_CC – 0.1			V
V_OL	Output low voltage	1-mA Load			0.1	V
I_OH	Output high current (Source)	V_CC = 3.3 V, V_O = 1.65 V		28		mA
I_OL	Output low current (Sink)	V_CC = 3.3 V, V_O = 1.65 V		28		mA
DUTY_CLK	Output duty cycle⁽⁹⁾	V_CC/2 to V_CC/2, F_CLK = 100 MHz, T = 25°C	45	50	55	%
T_R	Output rise time	20% to 80%, R_L = 50 Ω, CL = 5 pF		400		ps
T_F	Output fall time	80% to 20%, R_L = 50 Ω, CL = 5 pF		400		ps
DIGITAL OUTPUTS (Ftest/LD, Readback, GPoutX)
V_OH	High-level output voltage	I_OH = –500 µA	V_CC – 0.4			V
V_OL	Low-level output voltage	I_OL = 500 µA			0.4	V
DIGITAL INPUTS (SYNC)
V_IH	High-level input voltage		1.6		V_CC	V
V_IL	Low-level input voltage				0.4	V
DIGITAL INPUTS (CLKuWire, DATAuWire, LEuWire)
V_IH	High-level input voltage		1.6		V_CC	V
V_IL	Low-level input voltage				0.4	V
I_IH	High-level input current	V_IH = V_CC	5		25	µA
I_IL	Low-level input current	V_IL = 0	–5		5	µA

(1) If emitter resistors are placed on the OSCout1/1* pins, there will be a DC current to ground which will cause powerdown Icc to increase.

(2) Load conditions for output clocks: LVDS: 100 Ω differential. See Current Consumption and Power Dissipation Calculations for Icc for specific part configuration and how to calculate Icc for a specific design.

(3) In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input slew rate is reduced. However, the device will function at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to their common mode noise rejection. However, it is also recommended to use the highest possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs.

(4) F_OSCin maximum frequency guaranteed by characterization. Production tested at 200 MHz.

(5) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, L_{PLL_flicker}(f), which is dominant close to the carrier. Flicker noise has a 10 dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = L_{PLL_flicker}(10 kHz) - 20log(Fout / 1 GHz), where L_{PLL_flicker}(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure L_{PLL_flicker}(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). L_{PLL_flicker}(f) can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of L_{PLL_flicker}(f) and L_{PLL_flat}(f).

(6) A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, L_{PLL_flat}(f), is defined as: PN1HZ=L_{PLL_flat}(f) - 20log(N) - 10log(f_PD). L_{PLL_flat}(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz bandwidth and f_PD is the phase detector frequency of the synthesizer. L_{PLL_flat}(f) contributes to the total noise, L(f).

(7) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that the R30 register was last programmed, and still have the part stay in lock. The action of programming the R30 register, even to the same value, activates a frequency calibration routine. This implies the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reload the R30 register to ensure it stays in lock. Regardless of what temperature the part was initially programmed at, the temperature can never drift outside the frequency range of -40°C to 85°C without violating specifications.

(8) Equal loading and identical clock output configuration on each clock output is required for specification to be valid.

(9) Guaranteed by characterization.

(10) Jitter and phase noise data for 100 MHz, 156.25, and 312.5 MHz collected using an ECS crystal, part number ECS-200-20-30B-DU. Loop filter values are C1 = 220 pF, C2 = 18 nF, R2 = 820 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω. Charge pump current = 3.2 mA. LVPECL emitter resistors, R_e = 240 Ω. Reference doubler disabled. VCO frequency = 2500 MHz using a phase detector frequency = 20 MHz the loop bandwidth = 62 kHz and phase margin = 76°.

(11) Jitter and phase noise data for 106.25 MHz collected using an ECS crystal, part number ECS-200-20-30B-DU. Loop filter values are C1 = 220 pF, C2 = 18 nF, R2 = 820 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω. Charge pump current = 3.2 mA. LVPECL emitter resistors, R_e = 240 Ω. Reference doubler disabled. VCO frequency = 2550 MHz using a phase detector frequency = 10 MHz the loop bandwidth = 32 kHz and phase margin = 69°.

(12) Jitter and phase noise data for 622.08 MHz collected using a Vectron crystal, part number VXB1-1137-15M360. Loop filter values are C1 = 100 pF, C2 = 120 nF, R2 = 470 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω. Charge pump current = 3.2 mA. LVPECL emitter resistors, R_e = 240 Ω. Reference doubler enabled. VCO frequency = 2488.32 MHz using a phase detector frequency = 30.72 MHz the loop bandwidth = 54 kHz and phase margin = 86°.

(13) Refer to typical performance charts for output operation performance at higher frequencies than the minimum maximum output frequency.

(14) Jitter and phase noise data for 100 MHz, 156.25, and 312.5 MHz collected using a Wenzel crystal oscillator, part number 501–04623G. Loop filter values are C1 = 39 pF, C2 = 3.3 nF, R2 = 680 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω. Charge pump current = 3.2 mA. LVPECL emitter resistors, R_e = 240 Ω. Reference doubler disabled. VCO frequency = 2500 MHz using a phase detector frequency = 100 MHz the loop bandwidth = 80 kHz and phase margin = 60°.

(15) Jitter and phase noise data for 106.25 MHz collected using a Wenzel crystal oscillator, part number 501–04623G. Loop filter values are C1 = 39pF, C2 = 3.3 nF, R2 = 820Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω. Charge pump current = 3.2 mA. LVPECL emitter resistors, R_e = 240 Ω. Reference doubler disabled. VCO frequency = 2550 MHz using a phase detector frequency = 10 MHz the loop bandwidth = 80 kHz and phase margin = 60°.

(16) Jitter and phase noise data for 622.08 MHz collected using a Crystec oscillator, part number CVHD-950. Loop filter values are C1 = 39 pF, C2 = 3.3 nF, R2 = 680 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω. Charge pump current = 3.2 mA. LVPECL emitter resistors, R_e = 240 Ω. Reference doubler enabled. VCO frequency = 2488.32 MHz using a phase detector frequency = 30.72 MHz the loop bandwidth = 80 kHz and phase margin = 60°.