ZHCSHU9K September   2011  – December 2023 LMK03806

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 描述
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Differential Voltage Measurement Terminology
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Features Description
      1. 7.3.1 Serial MICROWIRE Timing Diagram and Terminology
      2. 7.3.2 Crystal Support With Buffered Outputs
      3. 7.3.3 Integrated Loop Filter Poles
      4. 7.3.4 Integrated VCO
      5. 7.3.5 Clock Distribution
        1. 7.3.5.1 CLKout DIvider
        2. 7.3.5.2 Programmable Output Type
        3. 7.3.5.3 Clock Output Synchronization
      6. 7.3.6 Default Start-Up Clocks
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 General Information
        1. 7.5.1.1 Special Programming Case for R0 to R5 for CLKoutX_Y_DIV > 25
        2. 7.5.1.2 Recommended Initial Programming Sequence
        3. 7.5.1.3 READBACK
          1. 7.5.1.3.1 Readback Example
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Crystal Interface
      2. 8.1.2 Driving OSCin Pins With a Single-Ended Source
      3. 8.1.3 Driving OSCin Pins With a Differential Source
      4. 8.1.4 Frequency Planning With the LMK03806
      5. 8.1.5 Configuring the PLL
        1. 8.1.5.1 Example PLL Configuration
      6. 8.1.6 Digital Lock Detect
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Device Selection
          1. 8.2.2.1.1 Clock Architect
          2. 8.2.2.1.2 Clock Design Tool
          3. 8.2.2.1.3 Calculation Using LCM
        2. 8.2.2.2 Device Configuration
        3. 8.2.2.3 PLL Loop Filter Design
          1. 8.2.2.3.1 Example Loop Filter Design
        4. 8.2.2.4 Other Device Specific Configuration
          1. 8.2.2.4.1 Digital Lock Detect
        5. 8.2.2.5 Device Programming
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 System Level Diagram
    4. 8.4 Best Design Practices
      1. 8.4.1 LVCMOS Complementary vs. Non-Complementary Operation
      2. 8.4.2 LVPECL Outputs
      3. 8.4.3 Sharing MICROWIRE (SPI) Lines
      4. 8.4.4 SYNC Pin
      5. 8.4.5 CLKout Vcc Pins
    5. 8.5 Power Supply Recommendations
      1. 8.5.1 Current Consumption and Power Dissipation Calculations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 接收文档更新通知
    4. 9.4 支持资源
    5. 9.5 Trademarks
    6. 9.6 静电放电警告
    7. 9.7 术语表
  11. 10Register Maps
    1. 10.1  Default Device Register Settings After Power On Reset
    2. 10.2  Register R0 TO R5
      1. 10.2.1 CLKoutX_Y_PD, Powerdown CLKoutX_Y Output Path
      2. 10.2.2 RESET
      3. 10.2.3 POWERDOWN
      4. 10.2.4 CLKoutX_Y_DIV, Clock Output Divide
    3. 10.3  Registers R6 TO R8
      1. 10.3.1 CLKoutX_TYPE
    4. 10.4  REGISTER R9
    5. 10.5  REGISTER R10
      1. 10.5.1 OSCout1_TYPE, LVPECL Output Amplitude Control
      2. 10.5.2 OSCout0_TYPE
      3. 10.5.3 EN_OSCoutX, OSCout Output Enable
      4. 10.5.4 OSCoutX_MUX, Clock Output Mux
      5. 10.5.5 OSCout_DIV, Oscillator Output Divide
    6. 10.6  REGISTER R11
      1. 10.6.1 NO_SYNC_CLKoutX_Y
      2. 10.6.2 SYNC_POL_INV
      3. 10.6.3 SYNC_TYPE
      4. 10.6.4 EN_PLL_XTAL
    7. 10.7  REGISTER R12
      1. 10.7.1 LD_MUX
      2. 10.7.2 LD_TYPE
      3. 10.7.3 SYNC_PLL_DLD
    8. 10.8  REGISTER R13
      1. 10.8.1 READBACK_TYPE
      2. 10.8.2 GPout0
    9. 10.9  REGISTER 14
      1. 10.9.1 GPout1
    10. 10.10 REGISTER 16
    11. 10.11 REGISTER 24
      1. 10.11.1 PLL_C4_LF, PLL Integrated Loop Filter Component
      2. 10.11.2 PLL_C3_LF, PLL Integrated Loop Filter Component
      3. 10.11.3 PLL_R4_LF, PLL Integrated Loop Filter Component
      4. 10.11.4 PLL_R3_LF, PLL Integrated Loop Filter Component
    12. 10.12 REGISTER 26
      1. 10.12.1 EN_PLL_REF_2X, PLL Reference Frequency Doubler
      2. 10.12.2 PLL_CP_GAIN, PLL Charge Pump Current
      3. 10.12.3 PLL_DLD_CNT
    13. 10.13 REGISTER 28
      1. 10.13.1 PLL_R, PLL R Divider
    14. 10.14 REGISTER 29
      1. 10.14.1 OSCin_FREQ, PLL Oscillator Input Frequency Register
      2. 10.14.2 PLL_N_CAL, PLL N Calibration Divider
    15. 10.15 REGISTER 30
      1. 10.15.1 PLL_P, PLL N Prescaler Divider
      2. 10.15.2 PLL_N, PLL N Divider
    16. 10.16 REGISTER 31
      1. 10.16.1 READBACK_ADDR
      2. 10.16.2 uWire_LOCK
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
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订购信息

10 Register Maps

Table 10-1 Provides the register map for device programming. At no time should registers be programmed to undefined values. Only valid register values should be written.

Table 10-1 Register Map
REGISTER313029282726252423222120191817161514131211109876543210
DATA [26:0]ADDRESS [4:0]
R0CLKout
0_1_PD		0000000000000RESET0CLKout0_1_DIV [15:5]00000
R1CLKout
2_3_PD		0000000000000POWERDOWN0CLKout2_3_DIV [15:5]00001
R2CLKout
4_5_PD		000000000000000CLKout4_5_DIV [15:5]00010
R3CLKout
6_7_PD		000000000000000CLKout6_7_DIV [15:5]00011
R4CLKout
8_9_PD		000000000000000CLKout8_9_DIV [15:5]00100
R5CLKout
10_11_PD		000000000000000CLKout10_11_DIV [15:5]00101
R6CLKout3_TYPE [31:28]CLKout2_TYPE [27:24]CLKout1_TYPE [23:20]CLKout0_TYPE [19:16]0000000000000110
R7CLKout7_TYPE [31:28]CLKout6_TYPE [27:24]CLKout5_TYPE [23:20]CLKout4_TYPE [19:16]0000000000000111
R8CLKout11_TYPE [31:28]CLKout10_TYPE [27:24]CLKout9_TYPE [23:20]CLKout8_TYPE [19:16]0000000000001000
R901010101010101010101010101001001
R10OSCout1
_TYPE
[31:30]		01OSCout0_TYPE [27:24]EN_OSCout1EN_OSCout0OSCout1_MUXOSCout0_MUX0OSCout_DIV
[18:16]		0100000000001010
R11001101NO_SYNC_CLKout10_11NO_SYNC_CLKout8_9NO_SYNC_CLKout6_7NO_SYNC_CLKout4_5NO_SYNC_CLKout2_3NO_SYNC_CLKout0_1000SYNC_POL_INV00SYNC_TYPE
[13:12]		000000EN_PLL_XTAL01011
R12LD_MUX [31:27]Ftest/LD
_TYPE
[26:24]		SYNC_PLL
_DLD		00011000000000001101100
R1300111READBACK
_TYPE
[26:24]		00000GPout0
[18:16]		1000000000001101
R1400000GPout1
[26:24]		000000000000000000001110
R1611000001010101010000010000010000
R24PLL_C4_LF
[31:28]		PLL_C3_LF
[27:24]		0PLL_R4_LF
[22:20]		0PLL_R3_LF
[18:16]		0000000000011000
R2610EN_PLL_
REF_2X		0PLL_CP
_GAIN
[27:26]		111010PLL_DLD_CNT
[19:6]		011010
R28PLL_R00000000000000011100
R2900000OSCin_FREQ
[26:24]		1PLL_N_CAL [22:5]11101
R3000000PLL_P0PLL_N [22:5]11110
R3100000000000READBACK_ADDR
[20:16]		0000000000uWire_LOCK11111
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