9.4.1 Dual PLL

Figure 52 illustrates the typical use case of the LMK0461x device family in dual-loop mode. In dual-loop mode the reference to PLL1 from CLKin0 or CLKin1. An external VCXO is used to provide feedback for the first PLL and a reference to the second PLL. This first PLL cleans the jitter with the VCXO by using a narrow loop bandwidth. The VCXO output may be buffered through the OSCout port. The VCXO is used as the reference to PLL2 and may be doubled using the frequency doubler. The internal VCO drives up to 8 divide or delay blocks which drive up to 10 clock outputs.

Holdover functionality is optionally available when the input reference clock is lost. Holdover works by fixing the tuning voltage of PLL1 to the VCXO.

Figure 52. Simplified Functional Block Diagram for Dual-Loop Mode