7.7 Clock Input Characteristics (OSCin)
3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;
1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40°C < TA < 85°C and TPCB ≤ 105°C. Typical values at VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, TA = 25°C, at the Recommended Operating Conditions and are not assured.
| PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
| fOSCin |
PLL2 reference input (1) |
Single-ended, AC-coupled (2) |
10 |
|
300 |
MHz |
| Differential, AC-coupled (3) |
10 |
|
600 |
| SLEWDIFF |
Differential input slew rate(4) |
20% to 80% |
0.2 |
6 |
|
V/ns |
| SLEWSE |
Single-ended input slew rate(4) |
20% to 80% |
0.1 |
3 |
|
V/ns |
| VOSCin |
Single-ended input voltage |
AC-coupled to OSCin;
OSCin* AC-coupled to Ground |
0.5 |
|
3.3 |
Vpp |
| VID,pp |
Peak-to-peak differential input voltage(5)
See Figure 9 |
AC-coupled |
0.4 |
|
3.3 |
Vpp |
| IDC |
Input duty cycle |
|
45% |
50% |
55% |
|
(1) FOSCin maximum frequency assured by characterization. Production tested at 122.88 MHz.
(4) To meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended differential slew rate for all input clocks is 3 V/ns; this is especially true for single-ended clocks. Phase noise performance begins to degrade as the clock input slew rate is reduced. However, the device functions at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) are less susceptible to degradation in phase noise performance at lower slew rates due to their common mode noise rejection. However, TI also recommends using the highest possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs.