ZHCSG17B
January 2017 – July 2019
LMK04610
PRODUCTION DATA.
1
特性
2
应用
3
说明
简化原理图
4
修订历史记录
5
Device Comparison Table
6
Pin Configuration and Functions
Pin Functions: LMK04610
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Digital Input and Output Characteristics (CLKin_SEL, STATUSx, SYNC, RESETN)
7.6
Clock Input Characteristics (CLKinX)
7.7
Clock Input Characteristics (OSCin)
7.8
PLL1 Specification Characteristics
7.9
PLL2 Specification Characteristics
7.10
Clock Output Type Characteristics (CLKoutX)
7.11
Oscillator Output Characteristics (OSCout)
7.12
Jitter and Phase Noise Characteristics for CLKoutX and OSCout
7.13
Clock Output Skew and Isolation Characteristics
7.14
Clock Output Delay Characteristics
7.15
DEFAULT POWER on RESET CLOCK OUTPUT Characteristics
7.16
Power Supply Characteristics
7.17
Typical Power Supply Noise Rejection Characteristics
7.18
SPI Interface Timing
7.19
Timing Diagram
7.20
Typical Characteristics
7.20.1
Clock Output AC Characteristics
8
Parameter Measurement Information
8.1
Differential Voltage Measurement Terminology
8.2
Output Termination Scheme
8.2.1
HSDS 4/6/8mA
8.2.2
HCSL
8.2.3
LVCMOS
9
Detailed Description
9.1
Overview
9.1.1
Jitter Cleaning
9.1.2
Two Redundant Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*)
9.1.3
VCXO Buffered Output
9.1.4
Frequency Holdover
9.1.5
Integrated Programmable PLL1 and PLL2 Loop Filter
9.1.6
Internal VCOs
9.1.7
Clock Distribution
9.1.7.1
Output Clock Divider
9.1.7.2
Output Clock Delay
9.1.7.3
Glitchless Half-Step and Glitchless Analog Delay
9.1.7.4
Programmable Output Formats
9.1.7.5
Clock Output SYNChronization
9.1.8
Status Pins
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*)
9.3.1.1
Input Clock Switching
9.3.1.1.1
Input Clock Switching – Register Select Mode
9.3.1.1.2
Input Clock Switching – Pin Select Mode (CLKin_SEL)
9.3.1.1.3
Input Clock Switching – Automatic Mode
9.3.1.2
Loss of Signal Detection – LOS
9.3.1.2.1
LOS – Assertion
9.3.1.2.2
LOS – Reference Clock Recovery
9.3.1.3
Driving CLKin and OSCin Inputs
9.3.1.3.1
Driving CLKin and OSCin Pins With a Differential Source
9.3.1.3.2
Driving CLKin and OSCin Pins With a Single-Ended Source
9.3.2
Clock Outputs (CLKoutX)
9.3.2.1
HCSL
9.3.2.2
HSDS
9.3.2.3
SYNC
9.3.2.4
Digital Delay
9.3.2.4.1
Fixed Digital Delay
9.3.2.4.2
Dynamic Digital Delay
9.3.2.5
Analog Delay
9.3.3
OSCout
9.3.3.1
Pin-Controlled OSCout Divider
9.3.4
STATUS0/1 and SYNC Pin Functions
9.3.4.1
Common STATUS0/1 and SYNC Pin Functions
9.3.4.2
Additional STATUS0 Pin Functions
9.3.4.3
Additional SYNC Pin Functions
9.3.5
PLL1 and PLL2
9.3.5.1
PLL1
9.3.5.1.1
PLL1 Proportional Modes
9.3.5.1.2
PLL1 Higher Order Poles
9.3.5.2
PLL2
9.3.5.2.1
PLL2 Divider
9.3.5.2.2
PLL2 Input Modes
9.3.5.2.3
PLL2 Loop Filter
9.3.5.2.4
PLL2 3rd Order Loop Filter
9.3.5.2.5
PLL2 Voltage Controlled Oscillator (VCO)
9.3.5.2.6
Examples of PLL2 Setting
9.3.5.3
Digital Lock Detect
9.3.5.3.1
Calculating Digital Lock Detect Frequency Accuracy
9.3.6
Holdover
9.3.6.1
Holdover Flowchart
9.3.6.2
Enable Holdover
9.3.6.2.1
Automatic Tracked CTRL_VCXO Holdover Mode
9.3.6.3
Enter Holdover
9.3.6.3.1
LOS_x Detect
9.3.6.3.2
PLL1 DLD Detect
9.3.6.3.3
CTRL_VCXO Rail Detect
9.3.6.3.3.1
Absolute Limits
9.3.6.3.3.2
Relative Limits
9.3.6.3.4
Manual Holdover Enable – Register Control
9.3.6.3.5
Manual Holdover Enable – Pin Control
9.3.6.3.6
Start-Up into Holdover
9.3.6.4
During Holdover
9.3.6.5
Exiting Holdover
9.3.6.6
Holdover Frequency Accuracy
9.3.6.7
Holdover Mode – Automatic Exit by LOS Deassertion
9.3.6.8
Holdover Mode – Automatic Exit of Holdover With Holdover Counter
9.3.7
JEDEC JESD204B
9.3.7.1
SYNC Pins
9.3.7.2
SYNC modes
9.3.7.3
SYSREF Modes
9.3.7.3.1
SYSREF Pulser
9.3.7.3.1.1
SPI Pulser Mode
9.3.7.3.1.2
Pin Pulser Mode
9.3.7.3.1.3
Multiple SYSREF Frequencies
9.3.7.3.2
Continuous SYSREF
9.3.7.3.3
SYSREF Request
9.3.7.4
How to Enable SYSREF
9.3.7.4.1
Setup Example 1: Pulser Mode, Pin Controlled
9.3.7.4.2
Setup Example 2: Pulser Mode, Spi Controlled
9.3.8
Zero Delay Mode (ZDM)
9.3.9
Power-Up Sequence
9.4
Device Functional Modes
9.4.1
Dual PLL
9.4.2
Single PLL
9.4.3
PLL2 Bypass
9.4.4
Clock Distribution
9.5
Programming
9.5.1
Recommended Programming Sequence
9.5.1.1
Readback
9.6
Register Maps
9.6.1
Register Map for Device Programming
9.6.2
Device Register Descriptions
9.6.2.1
CONFIGA
9.6.2.2
RESERVED1
9.6.2.3
RESERVED2
9.6.2.4
CHIP_TYPE
9.6.2.5
CHIP_ID_BY1
9.6.2.6
CHIP_ID_BY0
9.6.2.7
CHIP_VER
9.6.2.8
RESERVED3
9.6.2.9
RESERVED4
9.6.2.10
RESERVED5
9.6.2.11
RESERVED6
9.6.2.12
RESERVED7
9.6.2.13
VENDOR_ID_BY1
9.6.2.14
VENDOR_ID_BY0
9.6.2.15
RESERVED8
9.6.2.16
RESERVED9
9.6.2.17
STARTUP_CFG
9.6.2.18
STARTUP
9.6.2.19
DIGCLKCTRL
9.6.2.20
PLL2REFCLKDIV
9.6.2.21
GLBL_SYNC_SYSREF
9.6.2.22
CLKIN_CTRL0
9.6.2.23
CLKIN_CTRL1
9.6.2.24
CLKIN0CTRL
9.6.2.25
CLKIN1CTRL
9.6.2.26
CLKIN0RDIV_BY1
9.6.2.27
CLKIN0RDIV_BY0
9.6.2.28
CLKIN1RDIV_BY1
9.6.2.29
CLKIN1RDIV_BY0
9.6.2.30
CLKIN0LOS_REC_CNT
9.6.2.31
CLKIN0LOS_LAT_SEL
9.6.2.32
CLKIN1LOS_REC_CNT
9.6.2.33
CLKIN1LOS_LAT_SEL
9.6.2.34
CLKIN_SWCTRL0
9.6.2.35
CLKIN_SWCTRL1
9.6.2.36
CLKIN_SWCTRL2
9.6.2.37
OSCIN_CTRL
9.6.2.38
OSCOUT_CTRL
9.6.2.39
OSCOUT_DIV
9.6.2.40
OSCOUT_DRV
9.6.2.41
OUTCH_SWRST
9.6.2.42
OUTCH1CNTL0
9.6.2.43
OUTCH1CNTL1
9.6.2.44
OUTCH2CNTL0
9.6.2.45
OUTCH2CNTL1
9.6.2.46
OUTCH34CNTL0
9.6.2.47
OUTCH34CNTL1
9.6.2.48
OUTCH5CNTL0
9.6.2.49
OUTCH5CNTL1
9.6.2.50
OUTCH6CNTL0
9.6.2.51
OUTCH6CNTL1
9.6.2.52
OUTCH78CNTL0
9.6.2.53
OUTCH78CNTL1
9.6.2.54
OUTCH9CNTL0
9.6.2.55
OUTCH9CNTL1
9.6.2.56
OUTCH10CNTL0
9.6.2.57
OUTCH10CNTL1
9.6.2.58
OUTCH1DIV_BY1
9.6.2.59
OUTCH1DIV_BY0
9.6.2.60
OUTCH2DIV_BY1
9.6.2.61
OUTCH2DIV_BY0
9.6.2.62
OUTCH34DIV_BY1
9.6.2.63
OUTCH34DIV_BY0
9.6.2.64
OUTCH5DIV_BY1
9.6.2.65
OUTCH5DIV_BY0
9.6.2.66
OUTCH6DIV_BY1
9.6.2.67
OUTCH6DIV_BY0
9.6.2.68
OUTCH78DIV_BY1
9.6.2.69
OUTCH78DIV_BY0
9.6.2.70
OUTCH9DIV_BY1
9.6.2.71
OUTCH9DIV_BY0
9.6.2.72
OUTCH10DIV_BY1
9.6.2.73
OUTCH10DIV_BY0
9.6.2.74
OUTCH_DIV_INV
9.6.2.75
PLL1CTRL0
9.6.2.76
PLL1CTRL1
9.6.2.77
PLL1CTRL2
9.6.2.78
PLL1_SWRST
9.6.2.79
PLL1WNDWSIZE
9.6.2.80
PLL1STRCELL
9.6.2.81
PLL1CPSETTING
9.6.2.82
PLL1CPSETTING_FL
9.6.2.83
PLL1_HOLDOVER_CTRL1
9.6.2.84
PLL1_HOLDOVER_MAXCNT_BY3
9.6.2.85
PLL1_HOLDOVER_MAXCNT_BY2
9.6.2.86
PLL1_HOLDOVER_MAXCNT_BY1
9.6.2.87
PLL1_HOLDOVER_MAXCNT_BY0
9.6.2.88
PLL1_NDIV_BY1
9.6.2.89
PLL1_NDIV_BY0
9.6.2.90
PLL1_LOCKDET_CYC_CNT_BY2
9.6.2.91
PLL1_LOCKDET_CYC_CNT_BY1
9.6.2.92
PLL1_LOCKDET_CYC_CNT_BY0
9.6.2.93
PLL1_STRG_BY4
9.6.2.94
PLL1_STRG_BY3
9.6.2.95
PLL1_STRG_BY2
9.6.2.96
PLL1_STRG_BY1
9.6.2.97
PLL1_STRG_BY0
9.6.2.98
PLL1RCCLKDIV
9.6.2.99
PLL2_CTRL0
9.6.2.100
PLL2_CTRL1
9.6.2.101
PLL2_CTRL2
9.6.2.102
PLL2_SWRST
9.6.2.103
PLL2_LF_C4R4
9.6.2.104
PLL2_LF_C3R3
9.6.2.105
PLL2_CP_SETTING
9.6.2.106
PLL2_NDIV_BY1
9.6.2.107
PLL2_NDIV_BY0
9.6.2.108
PLL2_RDIV_BY1
9.6.2.109
PLL2_RDIV_BY0
9.6.2.110
PLL2_STRG_INIT_BY1
9.6.2.111
PLL2_STRG_INIT_BY0
9.6.2.112
RAILDET_UP
9.6.2.113
RAILDET_LOW
9.6.2.114
PLL2_AC_CTRL
9.6.2.115
PLL2_CURR_STOR_CELL
9.6.2.116
PLL2_AC_THRESHOLD
9.6.2.117
PLL2_AC_STRT_THRESHOLD
9.6.2.118
PLL2_AC_WAIT_CTRL
9.6.2.119
PLL2_AC_JUMPSTEP
9.6.2.120
PLL2_LD_WNDW_SIZE
9.6.2.121
PLL2_LD_WNDW_SIZE_INITIAL
9.6.2.122
PLL2_LOCKDET_CYC_CNT_BY2
9.6.2.123
PLL2_LOCKDET_CYC_CNT_BY1
9.6.2.124
PLL2_LOCKDET_CYC_CNT_BY0
9.6.2.125
PLL2_LOCKDET_CYC_CNT_INITIAL_BY2
9.6.2.126
PLL2_LOCKDET_CYC_CNT_INITIAL_BY1
9.6.2.127
PLL2_LOCKDET_CYC_CNT_INITIAL_BY0
9.6.2.128
IOCTRL_SPI0
9.6.2.129
IOCTRL_SPI1
9.6.2.130
IOTEST_SDIO
9.6.2.131
IOTEST_SCL
9.6.2.132
IOTEST_SCS
9.6.2.133
IOCTRL_STAT0
9.6.2.134
IOCTRL_STAT1
9.6.2.135
STAT1MUX
9.6.2.136
STAT0MUX
9.6.2.137
STATPLL2CLKDIV
9.6.2.138
IOTEST_STAT0
9.6.2.139
IOTEST_STAT1
9.6.2.140
IOCTRL_SYNC
9.6.2.141
DUMMY_REGISTER_1
9.6.2.142
IOCTRL_CLKINSEL1
9.6.2.143
IOTEST_CLKINSEL1
9.6.2.144
PLL1_TSTMODE
9.6.2.145
PLL2_CTRL
9.6.2.146
STATUS
9.6.2.147
PLL2_DLD_EN
9.6.2.148
PLL2_DUAL_LOOP
9.6.2.149
RESERVED10
9.6.2.150
CH1_DDLY_BY0
9.6.2.151
CH2_DDLY_BY0
9.6.2.152
CH34_DDLY_BY0
9.6.2.153
CH5_DDLY_BY0
9.6.2.154
CH6_DDLY_BY0
9.6.2.155
CH78_DDLY_BY0
9.6.2.156
CH9_DDLY_BY0
9.6.2.157
CH10_DDLY_BY0
9.6.2.158
OUTCH1_JESD_CTRL
9.6.2.159
OUTCH2_JESD_CTRL
9.6.2.160
OUTCH3_JESD_CTRL
9.6.2.161
OUTCH4_JESD_CTRL
9.6.2.162
OUTCH5_JESD_CTRL
9.6.2.163
OUTCH6_JESD_CTRL
9.6.2.164
OUTCH7_JESD_CTRL
9.6.2.165
OUTCH8_JESD_CTRL
9.6.2.166
OUTCH9_JESD_CTRL
9.6.2.167
OUTCH10_JESD_CTRL
9.6.2.168
CLKMUXVECTOR
9.6.2.169
OUTCH1CNTL2
9.6.2.170
OUTCH2CNTL2
9.6.2.171
OUTCH34CNTL2
9.6.2.172
OUTCH5CNTL2
9.6.2.173
OUTCH6CNTL2
9.6.2.174
OUTCH78CNTL2
9.6.2.175
OUTCH9CNTL2
9.6.2.176
OUTCH10CNTL2
9.6.2.177
OUTCH1_JESD_CTRL1
9.6.2.178
OUTCH2_JESD_CTRL1
9.6.2.179
OUTCH3_JESD_CTRL1
9.6.2.180
OUTCH4_JESD_CTRL1
9.6.2.181
OUTCH5_JESD_CTRL1
9.6.2.182
OUTCH6_JESD_CTRL1
9.6.2.183
OUTCH7_JESD_CTRL1
9.6.2.184
OUTCH8_JESD_CTRL1
9.6.2.185
OUTCH9_JESD_CTRL1
9.6.2.186
OUTCH10_JESD_CTRL1
9.6.2.187
SYSREF_PLS_CNT
9.6.2.188
SYNCMUX
9.6.2.189
IOTEST_SYNC
9.6.2.190
OUTCH_ZDM
9.6.2.191
PLL2_CTRL3
9.6.2.192
PLL1_HOLDOVER_CTRL0
9.6.2.193
IOCTRL_SYNC_1
9.6.2.194
OUTCH_TOP_JESD_CTRL
9.6.2.195
OUTCH_BOT_JESD_CTRL
9.6.2.196
OUTCH_JESD_CTRL1
9.6.2.197
PLL2_CTRL4
9.6.2.198
PLL2_CTRL5
9.6.2.199
PLL2_CTRL6
9.6.2.200
PLL2_CTRL7
10
Application and Implementation
10.1
Application Information
10.1.1
Digital Lock Detect Frequency Accuracy
10.1.1.1
Minimum Lock Time Calculation Example
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.2.1
PLL Loop Filter Design
10.2.2.2
Clock Output Assignment
10.2.2.3
Calculation Using LCM
10.2.2.4
Device Programming
10.2.2.5
Device Selection
10.2.2.6
Clock Architect
10.2.3
Application Curves
10.3
Do's and Don'ts
10.3.1
Pin Connection Recommendations
11
Power Supply Recommendations
11.1
Recommended Power Supply Connection
11.2
Current Consumption / Power Dissipation Calculations
12
Layout
12.1
Layout Guidelines
12.1.1
CLKin and OSCin
12.1.2
CLKout
12.2
Layout Example
13
器件和文档支持
13.1
器件支持
13.1.1
开发支持
13.1.1.1
时钟设计工具
13.1.1.2
时钟架构
13.1.1.3
TICS Pro
13.2
接收文档更新通知
13.3
社区资源
13.4
商标
13.5
静电放电警告
13.6
Glossary
14
机械、封装和可订购信息
封装选项
机械数据 (封装 | 引脚)
RTQ|56
MPQF168D
散热焊盘机械数据 (封装 | 引脚)
RTQ|56
QFND490A
订购信息
zhcsg17b_oa
zhcsg17b_pm
9.6.2.108
PLL2_RDIV_BY1
RESERVED. Return to
Register Map
.
Table 132.
Register – 0x75
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL2_RDIV[15:8]
RW
0x0
PLL2 R-Divider Value. PLL2 R-Divider configuration limited to bits [5..0].
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