10.1.1 Digital Lock Detect Frequency Accuracy

The digital lock detect circuit is used to determine PLL1 locked and PLL2 locked. A window size and lock count register are programmed to set a ppm frequency accuracy of reference to feedback signals of the PLL for each event to occur. When a PLL digital lock event occurs the PLL's digital lock detect is asserted true.

For a digital lock detect event to occur there must be a lock count number of a count frequency during which the time/phase error of the PLLX_R reference and PLLX_N feedback signal edges are within the user programmable window size. Because there must be at least lock count number of count frequency cycles, a minimum digital lock detect assert time can be calculated as lock count / count frequency where count frequency = PLL2 phase detector frequency. PLL2 lock time is the sum of the PLL2 Lock (Initial) + PLL2 Lock time.

By using Equation 1, values for a lock count and window size can be chosen to set the frequency accuracy required by the system in ppm before the digital lock detect event occurs:

Equation 1.

The effect of the lock count value is that it shortens the effective lock window size by dividing the window size by lock count.

If at any time the PLLX_R reference and PLLX_N feedback signals are outside the time window set by window size, then the lock count value is reset to 0.