11.1 Layout Guidelines

Power consumption of the LMK04816 can be high enough to require attention to thermal management. For reliability and performance reasons the die temperature must be limited to a maximum of 125°C. That is, as an estimate, T_A (ambient temperature) plus device power consumption times R_θJA must not exceed 125°C.

The package of the device has an exposed pad that provides the primary heat removal path as well as excellent electrical grounding to a printed-circuit-board. To maximize the removal of heat from the package a thermal land pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package.

A recommended land and via pattern is shown in Figure 43. More information on soldering WQFN, previously referred to as LLP packages, see Absolute Maximum Ratings for Soldering (SNOA549).

To minimize junction temperature, TI recommends that a simple heat sink be built into the PCB (if the ground plane layer is not exposed). This is done by including a copper area on the opposite side of the PCB from the device. This copper area may be plated or solder coated to prevent corrosion, but must not have conformal coating (if possible), which could provide thermal insulation. The vias shown in Figure 43 must connect these top and bottom copper layers and to the ground layer. These vias act as heat pipes to carry the thermal energy away from the device side of the board to where it can be more effectively dissipated. Avoid routing traces close to exposed ground pad to ensure proper thermal flow on the PCB.

Figure 43. Recommended Land and Via Pattern

11.2 Layout Example

Figure 44. LMK04816 Layout Example