SNAS605AS March   2013  – May 2020 LMK04821 , LMK04826 , LMK04828

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Device Comparison Table
    1. 5.1 Device Configuration Information
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Interface Timing
    7. 7.7 Typical Characteristics – Clock Output AC Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Charge Pump Current Specification Definitions
      1. 8.1.1 Charge Pump Output Current Magnitude Variation Vs. Charge Pump Output Voltage
      2. 8.1.2 Charge Pump Sink Current Vs. Charge Pump Output Source Current Mismatch
      3. 8.1.3 Charge Pump Output Current Magnitude Variation Vs. Ambient Temperature
    2. 8.2 Differential Voltage Measurement Terminology
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1  Jitter Cleaning
      2. 9.1.2  JEDEC JESD204B Support
      3. 9.1.3  Three PLL1 Redundant Reference Inputs
      4. 9.1.4  VCXO/Crystal Buffered Output
      5. 9.1.5  Frequency Holdover
      6. 9.1.6  PLL2 Integrated Loop Filter Poles
      7. 9.1.7  Internal VCOs
        1. 9.1.7.1 VCO1 Divider (LMK04821 only)
      8. 9.1.8  External VCO Mode
      9. 9.1.9  Clock Distribution
        1. 9.1.9.1 Device Clock Divider
        2. 9.1.9.2 SYSREF Clock Divider
        3. 9.1.9.3 Device Clock Delay
        4. 9.1.9.4 SYSREF Delay
        5. 9.1.9.5 Glitchless Half Step and Glitchless Analog Delay
        6. 9.1.9.6 Programmable Output Formats
        7. 9.1.9.7 Clock Output Synchronization
      10. 9.1.10 Zero-Delay
      11. 9.1.11 Status Pins
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 SYNC/SYSREF
      2. 9.3.2 JEDEC JESD204B
        1. 9.3.2.1 How To Enable SYSREF
          1. 9.3.2.1.1 Setup of SYSREF Example
          2. 9.3.2.1.2 SYSREF_CLR
        2. 9.3.2.2 SYSREF Modes
          1. 9.3.2.2.1 SYSREF Pulser
          2. 9.3.2.2.2 Continuous SYSREF
          3. 9.3.2.2.3 SYSREF Request
      3. 9.3.3 Digital Delay
        1. 9.3.3.1 Fixed Digital Delay
          1. 9.3.3.1.1 Fixed Digital Delay Example
        2. 9.3.3.2 Dynamic Digital Delay
        3. 9.3.3.3 Single and Multiple Dynamic Digital Delay Example
      4. 9.3.4 SYSREF to Device Clock Alignment
      5. 9.3.5 Input Clock Switching
        1. 9.3.5.1 Input Clock Switching - Manual Mode
        2. 9.3.5.2 Input Clock Switching - Pin Select Mode
        3. 9.3.5.3 Input Clock Switching - Automatic Mode
      6. 9.3.6 Digital Lock Detect
      7. 9.3.7 Holdover
        1. 9.3.7.1 Enable Holdover
          1. 9.3.7.1.1 Fixed (Manual) CPout1 Holdover Mode
          2. 9.3.7.1.2 Tracked CPout1 Holdover Mode
        2. 9.3.7.2 Entering Holdover
        3. 9.3.7.3 During Holdover
        4. 9.3.7.4 Exiting Holdover
        5. 9.3.7.5 Holdover Frequency Accuracy and DAC Performance
        6. 9.3.7.6 Holdover Mode - Automatic Exit of Holdover
    4. 9.4 Device Functional Modes
      1. 9.4.1 Dual PLL
      2. 9.4.2 Zero-Delay Dual PLL
      3. 9.4.3 Single-Loop Mode
      4. 9.4.4 Single-Loop Mode With External VCO
      5. 9.4.5 Distribution Mode
    5. 9.5 Programming
      1. 9.5.1 Recommended Programming Sequence
        1. 9.5.1.1 SPI LOCK
        2. 9.5.1.2 SYSREF_CLR
        3. 9.5.1.3 RESET Pin
    6. 9.6 Register Maps
      1. 9.6.1 Register Map for Device Programming
    7. 9.7 Device Register Descriptions
      1. 9.7.1 System Functions
        1. 9.7.1.1 RESET, SPI_3WIRE_DIS
        2. 9.7.1.2 POWERDOWN
        3. 9.7.1.3 ID_DEVICE_TYPE
        4. 9.7.1.4 ID_PROD[15:8], ID_PROD
        5. 9.7.1.5 ID_MASKREV
        6. 9.7.1.6 ID_VNDR[15:8], ID_VNDR
      2. 9.7.2 (0x100 - 0x138) Device Clock and SYSREF Clock Output Controls
        1. 9.7.2.1 CLKoutX_Y_ODL, CLKoutX_Y_IDL, DCLKoutX_DIV
        2. 9.7.2.2 DCLKoutX_DDLY_CNTH, DCLKoutX_DDLY_CNTL
        3. 9.7.2.3 DCLKoutX_ADLY, DCLKoutX_ADLY_MUX, DCLKout_MUX
        4. 9.7.2.4 DCLKoutX_HS, SDCLKoutY_MUX, SDCLKoutY_DDLY, SDCLKoutY_HS
        5. 9.7.2.5 SDCLKoutY_ADLY_EN, SDCLKoutY_ADLY
        6. 9.7.2.6 DCLKoutX_DDLY_PD, DCLKoutX_HSg_PD, DCLKout_ADLYg_PD, DCLKout_ADLY_PD, DCLKoutX_Y_PD, SDCLKoutY_DIS_MODE, SDCLKoutY_PD
        7. 9.7.2.7 SDCLKoutY_POL, SDCLKoutY_FMT, DCLKoutX_POL, DCLKoutX_FMT
      3. 9.7.3 SYSREF, SYNC, and Device Config
        1. 9.7.3.1  VCO_MUX, OSCout_MUX, OSCout_FMT
        2. 9.7.3.2  SYSREF_CLKin0_MUX, SYSREF_MUX
        3. 9.7.3.3  SYSREF_DIV[12:8], SYSREF_DIV[7:0]
        4. 9.7.3.4  SYSREF_DDLY[12:8], SYSREF_DDLY[7:0]
        5. 9.7.3.5  SYSREF_PULSE_CNT
        6. 9.7.3.6  PLL2_NCLK_MUX, PLL1_NCLK_MUX, FB_MUX, FB_MUX_EN
        7. 9.7.3.7  PLL1_PD, VCO_LDO_PD, VCO_PD, OSCin_PD, SYSREF_GBL_PD, SYSREF_PD, SYSREF_DDLY_PD, SYSREF_PLSR_PD
        8. 9.7.3.8  DDLYdSYSREF_EN, DDLYdX_EN
        9. 9.7.3.9  DDLYd_STEP_CNT
        10. 9.7.3.10 SYSREF_CLR, SYNC_1SHOT_EN, SYNC_POL, SYNC_EN, SYNC_PLL2_DLD, SYNC_PLL1_DLD, SYNC_MODE
        11. 9.7.3.11 SYNC_DISSYSREF, SYNC_DISX
        12. 9.7.3.12 Fixed Registers (0x145, 0x171 - 0x172)
      4. 9.7.4 (0x146 - 0x149) CLKin Control
        1. 9.7.4.1 CLKin2_EN, CLKin1_EN, CLKin0_EN, CLKin2_TYPE, CLKin1_TYPE, CLKin0_TYPE
        2. 9.7.4.2 CLKin_SEL_POL, CLKin_SEL_MODE, CLKin1_OUT_MUX, CLKin0_OUT_MUX
        3. 9.7.4.3 CLKin_SEL0_MUX, CLKin_SEL0_TYPE
        4. 9.7.4.4 SDIO_RDBK_TYPE, CLKin_SEL1_MUX, CLKin_SEL1_TYPE
      5. 9.7.5 RESET_MUX, RESET_TYPE
      6. 9.7.6 (0x14B - 0x152) Holdover
        1. 9.7.6.1 LOS_TIMEOUT, LOS_EN, TRACK_EN, HOLDOVER_FORCE, MAN_DAC_EN, MAN_DAC[9:8]
        2. 9.7.6.2 MAN_DAC[9:8], MAN_DAC[7:0]
        3. 9.7.6.3 DAC_TRIP_LOW
        4. 9.7.6.4 DAC_CLK_MULT, DAC_TRIP_HIGH
        5. 9.7.6.5 DAC_CLK_CNTR
        6. 9.7.6.6 CLKin_OVERRIDE, HOLDOVER_PLL1_DET, HOLDOVER_LOS_DET, HOLDOVER_VTUNE_DET, HOLDOVER_HITLESS_SWITCH, HOLDOVER_EN
        7. 9.7.6.7 HOLDOVER_DLD_CNT[13:8], HOLDOVER_DLD_CNT[7:0]
      7. 9.7.7 (0x153 - 0x15F) PLL1 Configuration
        1. 9.7.7.1 CLKin0_R[13:8], CLKin0_R[7:0]
        2. 9.7.7.2 CLKin1_R[13:8], CLKin1_R[7:0]
        3. 9.7.7.3 CLKin2_R[13:8], CLKin2_R[7:0]
        4. 9.7.7.4 PLL1_N
        5. 9.7.7.5 PLL1_WND_SIZE, PLL1_CP_TRI, PLL1_CP_POL, PLL1_CP_GAIN
        6. 9.7.7.6 PLL1_DLD_CNT[13:8], PLL1_DLD_CNT[7:0]
        7. 9.7.7.7 PLL1_R_DLY, PLL1_N_DLY
        8. 9.7.7.8 PLL1_LD_MUX, PLL1_LD_TYPE
      8. 9.7.8 (0x160 - 0x16E) PLL2 Configuration
        1. 9.7.8.1 PLL2_R[11:8], PLL2_R[7:0]
        2. 9.7.8.2 PLL2_P, OSCin_FREQ, PLL2_XTAL_EN, PLL2_REF_2X_EN
        3. 9.7.8.3 PLL2_N_CAL
        4. 9.7.8.4 PLL2_FCAL_DIS, PLL2_N
        5. 9.7.8.5 PLL2_WND_SIZE, PLL2_CP_GAIN, PLL2_CP_POL, PLL2_CP_TRI
        6. 9.7.8.6 SYSREF_REQ_EN, PLL2_DLD_CNT
        7. 9.7.8.7 PLL2_LF_R4, PLL2_LF_R3
        8. 9.7.8.8 PLL2_LF_C4, PLL2_LF_C3
        9. 9.7.8.9 PLL2_LD_MUX, PLL2_LD_TYPE
      9. 9.7.9 (0x16F - 0x1FFF) Misc Registers
        1. 9.7.9.1  PLL2_PRE_PD, PLL2_PD
        2. 9.7.9.2  VCO1_DIV
        3. 9.7.9.3  OPT_REG_1
        4. 9.7.9.4  OPT_REG_2
        5. 9.7.9.5  RB_PLL1_LD_LOST, RB_PLL1_LD, CLR_PLL1_LD_LOST
        6. 9.7.9.6  RB_PLL2_LD_LOST, RB_PLL2_LD, CLR_PLL2_LD_LOST
        7. 9.7.9.7  RB_DAC_VALUE(MSB), RB_CLKinX_SEL, RB_CLKinX_LOS
        8. 9.7.9.8  RB_DAC_VALUE
        9. 9.7.9.9  RB_HOLDOVER
        10. 9.7.9.10 SPI_LOCK
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Digital Lock Detect Frequency Accuracy
      1. 10.2.1 Minimum Lock Time Calculation Example
    3. 10.3 Driving CLKin and OSCin Inputs
      1. 10.3.1 Driving CLKin and OSCin Pins With a Differential Source
      2. 10.3.2 Driving CLKin and OSCin Pins With a Single-Ended Source
    4. 10.4 Output Termination and Biasing
      1. 10.4.1 LVPECL
      2. 10.4.2 LVDS/HSDS
    5. 10.5 Typical Applications
      1. 10.5.1 Design Example
        1. 10.5.1.1 Design Requirements
        2. 10.5.1.2 Detailed Design Procedure
          1. 10.5.1.2.1 Device Configuration and Simulation - PLLatinum Sim
          2. 10.5.1.2.2 Device Programming
        3. 10.5.1.3 Application Curves
    6. 10.6 System Examples
      1. 10.6.1 System Level Diagram
    7. 10.7 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Pin Connection Recommendations
      1. 11.1.1 VCC Pins and Decoupling
        1. 11.1.1.1 Clock Output Supplies
        2. 11.1.1.2 Low-Crosstalk Supplies
        3. 11.1.1.3 PLL2 Supplies
        4. 11.1.1.4 Clock Input Supplies
        5. 11.1.1.5 Unused Clock Inputs/Outputs
    2. 11.2 Current Consumption / Power Dissipation Calculations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Thermal Management
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
        1. 13.1.1.1 PLLatinum Sim
        2. 13.1.1.2 TICS Pro
    2. 13.2 Related Links
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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9.6.1 Register Map for Device Programming

Table 11 provides the register map for device programming. Any register can be read from the same data address it is written to.

Table 11. LMK0482x Register Map

ADDRESS DATA
[11:0] 7 6 5 4 3 2 1 0
0x000 RESET 0 0 SPI_3WIRE
_DIS		 0 0 0 0
0x002 0 0 0 0 0 0 0 POWER
DOWN
0x003 ID_DEVICE_TYPE
0x004 ID_PROD[15:8]
0x005 ID_PROD[7:0]
0x006 ID_MASKREV
0x00C ID_VNDR[15:8]
0x00D ID_VNDR[7:0]
0x100 0 CLKout0_1
_ODL		 CLKout0_1
_IDL		 DCLKout0_DIV
0x101 DCLKout0_DDLY_CNTH DCLKout0_DDLY_CNTL
0x103 DCLKout0_ADLY DCLKout0_
ADLY_MUX		 DCLKout0_MUX
0x104 0 DCLKout0
_HS		 SDCLKout1
_MUX		 SDCLKout1_DDLY SDCLKout1
_HS
0x105 0 0 0 SDCLKout1_
ADLY_EN		 SDCLKout1_ADLY
0x106 DCLKout0
_ DDLY_PD		 DCLKout0
_ HSg_PD		 DCLKout0
_ ADLYg_PD		 DCLKout0
_ADLY _PD		 CLKout0_1
_PD		 SDCLKout1_DIS_MODE SDCLKout1
_PD
0x107 SDCLKout1
_POL		 CLKout1_FMT DCLKout0
_POL		 CLKout0_FMT
0x108 0 CLKout2_3
_ODL		 CLKout2_3
_IDL		 DCLKout2_DIV
0x109 DCLKout2_DDLY_CNTH DCLKout2_DDLY_CNTL
0x10B DCLKout2_ADLY DCLKout2_
ADLY_MUX		 DCLKout2_MUX
0x10C 0 DCLKout2
_HS		 SDCLKout3
_MUX		 SDCLKout3_DDLY SDCLKout3
_HS
0x10D 0 0 0 SDCLKout3
_ ADLY_EN		 SDCLKout3_ADLY
0x10E DCLKout2
_ DDLY_PD		 DCLKout2
_ HSg_PD		 DCLKout2
_ ADLYg_PD		 DCLKout2
_ADLY _PD		 CLKout2_3
_PD		 SDCLKout3_DIS_MODE SDCLKout3
_PD
0x10F SDCLKout3
_POL		 CLKout3_FMT DCLKout2
_POL		 CLKout2_FMT
0x110 0 CLKout4_5
_ODL		 CLKout4_5
_IDL		 DCLKout4_DIV
0x111 DCLKout4_DDLY_CNTH DCLKout4_DDLY_CNTL
0x113 DCLKout4_ADLY DCLKout4_
ADLY_MUX		 DCLKout4_MUX
0x114 0 DCLKout4
_HS		 SDCLKout5
_MUX		 SDCLKout5_DDLY SDCLKout5
_HS
0x115 0 0 0 SDCLKout5
_ ADLY_EN		 SDCLKout5_ADLY
0x116 DCLKout4
_ DDLY_PD		 DCLKout4
_ HSg_PD		 DCLKout4
_ ADLYg_PD		 DCLKout4
_ADLY _PD		 CLKout4_5
_PD		 SDCLKout5_DIS_MODE SDCLKout5
_PD
0x117 SDCLKout5
_POL		 CLKout5_FMT DCLKout4
_POL		 CLKout4_FMT
0x118 0 CLKout6_7
_ODL		 CLKout6_8
_IDL		 DCLKout6_DIV
0x119 DCLKout6_DDLY_CNTH DCLKout6_DDLY_CNTL
0x11B DCLKout6_ADLY DCLKout6_
ADLY_MUX		 DCLKout6_MUX
0x11C 0 DCLKout6
_HS		 SDCLKout7
_MUX		 SDCLKout7_DDLY SDCLKout7
_HS
0x11D 0 0 0 SDCLKout7
_ ADLY_EN		 SDCLKout7_ADLY
0x11E DCLKout6
_ DDLY_PD		 DCLKout6
_ HSg_PD		 DCLKout6
_ ADLYg_PD		 DCLKout6
_ADLY _PD		 CLKout6_7
_PD		 SDCLKout7_DIS_MODE SDCLKout7
_PD
0x11F SDCLKout7
_POL		 CLKout7
_FMT		 DCLKout6
_POL		 CLKout6_FMT
0x120 0 CLKout8_9
_ODL		 CLKout8_9
_IDL		 DCLKout8_DIV
0x121 DCLKout8_DDLY_CNTH DCLKout8_DDLY_CNTL
0x123 DCLKout8_ADLY DCLKout8
_ ADLY_MUX		 DCLKout8_MUX
0x124 0 DCLKout8
_HS		 SDCLKout9
_MUX		 SDCLKout9_DDLY SDCLKout9
_HS
0x125 0 0 0 SDCLKout9
_ ADLY_EN		 SDCLKout9_ADLY
0x126 DCLKout8
_ DDLY_PD		 DCLKout8
_ HSg_PD		 DCLKout8
_ ADLYg_PD		 DCLKout8
_ADLY _PD		 CLKout8_9
_PD		 SDCLKout9_DIS_MODE SDCLKout9
_PD
0x127 SDCLKout9
_POL		 CLKout9_FMT DCLKout8
_POL		 CLKout8_FMT
0x128 0 CLKout10
_11 _ODL		 CLKout10
_11_IDL		 DCLKout10_DIV
0x129 DCLKout10_DDLY_CNTH DCLKout10_DDLY_CNTL
0x12B DCLKout10_ADLY DCLKout10
_ ADLY_MUX		 DCLKout10_MUX
0x12C 0 DCLKout10
_HS		 SDCLKout11
_MUX		 SDCLKout11_DDLY SDCLKout11
_HS
0x12D 0 0 0 SDCKLout11
_ ADLY_EN		 SDCLKout11_ADLY
0x12E DCLKout10
_ DDLY_PD		 DCLKout10
_ HSg_PD		 DLCLKout10
_ ADLYg_PD		 DCLKout10
_ ADLY_PD		 CLKout10
_11_PD		 SDCLKout11_DIS_MODE SDCLKout11
_PD
0x12F SDCLKout11
_POL		 CLKout11_FMT DCLKout10
_POL		 CLKout10_FMT
0x130 0 CLKout12
_13 _ODL		 CLKout12
_13_IDL		 DCLKout12_DIV
0x131 DCLKout12_DDLY_CNTH DCLKout12_DDLY_CNTL
0x133 DCLKout12_ADLY DCLKout12_
ADLY_MUX		 DCLKout12_MUX
0x134 0 DCLKout12
_HS		 SDCLKout13
_MUX		 SDCLKout13_DDLY SDCLKout13
_HS
0x135 0 0 0 SDCLKout13
_ ADLY_EN		 SDCLKout13_ADLY
0x136 DCLKout12
_ DDLY_PD		 DCLKout12
_ HSg_PD		 DCLKout12
_ ADLYg_PD		 DCLKout12
_ ADLY_PD		 CLKout12
_13_PD		 SDCLKout13_DIS_MODE SDCLKout13
_PD
0x137 SDCLKout13
_POL		 CLKout13_FMT DCLKout12
_POL		 CLKout12_FMT
0x138 0 VCO_MUX OSCout
_MUX		 OSCout_FMT
0x139 0 0 0 0 0 SYSREF_
CLKin0_MUX		 SYSREF_MUX
0x13A 0 0 0 SYSREF_DIV[12:8]
0x13B SYSREF_DIV[7:0]
0x13C 0 0 0 SYSREF_DDLY[12:8]
0x13D SYSREF_DDLY[7:0]
0x13E 0 0 0 0 0 0 SYSREF_PULSE_CNT
0x13F 0 0 0 PLL2_NCLK
_MUX		 PLL1_NCLK
_MUX		 FB_MUX FB_MUX
_EN
0x140 PLL1_PD VCO_LDO_PD VCO_PD OSCin_PD SYSREF_GBL
_PD		 SYSREF_PD SYSREF
_DDLY_PD		 SYSREF
_PLSR_PD
0x141 DDLYd_
SYSREF_EN		 DDLYd12
_EN		 DDLYd10
_EN		 DDLYd7_EN DDLYd6_EN DDLYd4_EN DDLYd2_EN DDLYd0_EN
0x142 0 0 0 DDLYd_STEP_CNT
0x143 SYSREF_DDLY
_CLR		 SYNC_1SHOT
_EN		 SYNC_POL SYNC_EN SYNC_PLL2
_DLD		 SYNC_PLL1
_DLD		 SYNC_MODE
0x144 SYNC
_DISSYSREF		 SYNC_DIS12 SYNC_DIS10 SYNC_DIS8 SYNC_DIS6 SYNC_DIS4 SYNC_DIS2 SYNC_DIS0
0x145 0 1 1 1 1 1 1 1
0x146 0 0 CLKin2_EN CLKin1_EN CLKin0_EN CLKin2_TYPE CLKin1_TYPE CLKin0_TYPE
0x147 CLKin_SEL
_POL		 CLKin_SEL_MODE CLKin1_OUT_MUX CLKin0_OUT_MUX
0x148 0 0 CLKin_SEL0_MUX CLKin_SEL0_TYPE
0x149 0 SDIO_RDBK
_TYPE		 CLKin_SEL1_MUX CLKin_SEL1_TYPE
0x14A 0 0 RESET_MUX RESET_TYPE
0x14B LOS_TIMEOUT LOS_EN TRACK_EN HOLDOVER
_ FORCE		 MAN_DAC
_EN		 MAN_DAC[9:8]
0x14C MAN_DAC[7:0]
0x14D 0 0 DAC_TRIP_LOW
0x14E DAC_CLK_MULT DAC_TRIP_HIGH
0x14F DAC_CLK_CNTR
0x150 0 CLKin
_OVERRIDE		 0 HOLDOVER
_ PLL1_DET		 HOLDOVER
_LOS _DET		 HOLDOVER
_VTUNE_DET		 HOLDOVER
_HITLESS
_SWITCH		 HOLDOVER
_EN
0x151 0 0 HOLDOVER_DLD_CNT[13:8]
0x152 HOLDOVER_DLD_CNT[7:0]
0x153 0 0 CLKin0_R[13:8]
0x154 CLKin0_R[7:0]
0x155 0 0 CLKin1_R[13:8]
0x156 CLKin1_R[7:0]
0x157 0 0 CLKin2_R[13:8]
0x158 CLKin2_R[7:0]
0x159 0 0 PLL1_N[13:8]
0x15A PLL1_N[7:0]
0x15B PLL1_WND_SIZE PLL1
_CP_TRI		 PLL1
_CP_POL		 PLL1_CP_GAIN
0x15C 0 0 PLL1_DLD_CNT[13:8]
0x15D PLL1_DLD_CNT[7:0]
0x15E 0 0 PLL1_R_DLY PLL1_N_DLY
0x15F PLL1_LD_MUX PLL1_LD_TYPE
0x160 0 0 0 0 PLL2_R[11:8]
0x161 PLL2_R[7:0]
0x162 PLL2_P OSCin_FREQ PLL2
_XTAL_EN		 PLL2
_REF_2X_EN
0x163 0 0 0 0 0 0 PLL2_N_CAL[17:16]
0x164 PLL2_N_CAL[15:8]
0x165 PLL2_N_CAL[7:0]
0x166 0 0 0 0 0 PLL2_FCAL
_DIS		 PLL2_N[17:16]
0x167 PLL2_N[15:8]
0x168 PLL2_N[7:0]
0x169 0 PLL2_WND_SIZE PLL2_CP_GAIN PLL2
_CP_POL		 PLL
2_CP_TRI		 1
0x16A 0 SYSREF_REQ_EN PLL2_DLD_CNT[15:8]
0x16B PLL2_DLD_CNT[7:0]
0x16C 0 0 PLL2_LF_R4 PLL2_LF_R3
0x16D PLL2_LF_C4 PLL2_LF_C3
0x16E PLL2_LD_MUX PLL2_LD_TYPE
0x171 1 0 1 0 1 0 1 0
0x172 0 0 0 0 0 0 1 0
0x173 0 PLL2_PRE_PD PLL2_PD 0 0 0 0 0
0x174 0 0 0 VCO1_DIV
0x17C OPT_REG_1
0x17D OPT_REG_2
0x182 0 0 0 0 0 RB_PLL1_
LD_LOST		 RB_PLL1_LD CLR_PLL1_
LD_LOST
0x183 0 0 0 0 0 RB_PLL2_
LD_LOST		 RB_PLL2_LD CLR_PLL2_
LD_LOST
0x184 RB_DAC_VALUE[9:8] RB_CLKin2_
SEL		 RB_CLKin1_
SEL		 RB_CLKin0_
SEL		 X RB_CLKin1_
LOS		 RB_CLKin0_
LOS
0x185 RB_DAC_VALUE[7:0]
0x188 0 0 0 RB_
HOLDOVER		 X X X X
0x1FFD SPI_LOCK[23:16]
0x1FFE SPI_LOCK[15:8]
0x1FFF SPI_LOCK[7:0]
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