9.3.2.1.1 Setup of SYSREF Example

The following procedure is a programming example for a system operating with a 3000-MHz VCO frequency. Use DCLKout0 and DCLKout2 to drive converters at 1500 MHz. Use DCLKout4 to drive an FPGA at 150 MHz. Synchronize the converters and FPGA using two SYSREF pulses at 10 MHz.

1. Program registers 0x000 to 0x1fff as desired. Key to prepare for SYSREF operations (see Recommended Programming Sequence):
   1. Prepare for manual SYNC: SYNC_POL = 0, SYNC_MODE = 1, SYSREF_MUX = 0
   2. Setup output dividers as per example: DCLKout0_DIV and DCLKout2_DIV = 2 for frequency of 1500 MHz. DCLKout4_DIV = 20 for frequency of 150 MHz.
   3. Setup output dividers as per example: SYSREF_DIV = 300 for 10 MHz SYSREF
   4. Setup SYSREF: SYSREF_PD = 0, SYSREF_DDLY_PD = 0, DCLKout0_DDLY_PD = 0, DCLKout2_DDLY_PD = 0, DCLKout4_DDLY_PD = 0, SYNC_EN = 1, SYSREF_PLSR_PD = 0, SYSREF_PULSE_CNT = 1 (2 pulses). SDCLKout1_PD = 0, SDCLKout3_PD = 0
   5. Clear Local SYSREF DDLY: SYSREF_CLR = 1.
2. Establish deterministic phase relationships between SYSREF and the device clock for JESD204B:
   1. Set device clock and SYSREF divider digital delays: DCLKout0_DDLY_CNTH, DCLKout0_DDLY_CNTL, DCLKout2_DDLY_CNTH, DCLKout2_DDLY_CNTL, DCLKout4_DDLY_CNTH, DCLKout4_DDLY_CNTL, SYSREF_DDLY.
   2. Set device clock digital delay half steps: DCLKout0_HS, DCLKout2_HS, DCLKout4_HS.
   3. Set SYSREF clock digital delay as required to achieve known phase relationships: SDCLKout1_DDLY, SDCLKout3_DDLY, SDCLKout5_DDLY.
   4. To allow SYNC to effect dividers: SYNC_DIS0 = 0, SYNC_DIS2 = 0, SYNC_DIS4 = 0, SYNC_DISSYSREF = 0
   5. Perform SYNC by toggling SYNC_POL = 1, then SYNC_POL = 0.
3. When the dividers are synchronized, disable SYNC from resetting these dividers. It is not desired for SYSREF to reset it's own divider or the dividers of the output clocks.
   1. Prevent SYSREF from affecting dividers: SYNC_DIS0 = 1, SYNC_DIS2 = 1, SYNC_DIS4 = 1, SYNC_DISSYSREF = 1.
4. Release reset of local SYSREF digital delay.
   1. SYSREF_CLR = 0. Note this bit needs to be set for only 15 clock distribution path cycles after SYSREF_PD = 0.
5. Set SYSREF operation.
   1. Allow pin SYNC event to start pulser: SYNC_MODE = 2.
   2. Select pulser as SYSREF signal: SYSREF_MUX = 2.
6. After the procedure is complete, asserting the SYNC pin or toggling SYNC_POL results in a series of 2 SYSREF pulses.