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SNAS703 April 2017 LMK04828-EP

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9 Detailed Description

9.1 Overview

The LMK04828-EP device is very flexible in meeting many application requirements. The typical use case for the LMK04828-EP is as a cascaded dual loop jitter cleaner for JESD204B systems. However, traditional (non-JESD204B) systems are possible with use of the large SYSREF divider to produce a low frequency. Note that while the Device Clock outputs (DCLKoutX) do not provide LVCMOS outputs, the OSCout may be used to provide LVCMOS outputs at DCLKout6 or DCLKout8 frequency using the feedback mux.

In addition to dual loop operation, by powering down various blocks the LMK04828-EP may be configured for single loop or clock distribution modes also.

9.1.1 Jitter Cleaning

The dual loop PLL architecture of the LMK04828-EP provides the lowest jitter performance over a wide range of output frequencies and phase noise integration bandwidths for clock inputs with unknown signal quality or low frequency. The first stage PLL (PLL1) is driven by an external reference clock and uses an external VCXO or tunable crystal to provide a frequency accurate, low phase noise reference clock for the second stage frequency multiplication PLL (PLL2).

PLL1 uses a narrow loop bandwidth (typically 10 Hz to 300 Hz) to retain the frequency accuracy of the reference clock input signal while at the same time suppressing the higher offset frequency phase noise that the reference clock may have accumulated along its path or from other circuits. This “cleaned” reference clock provides the reference input to PLL2.

The low phase noise reference provided to PLL2 allows PLL2 to operate with a wide loop bandwidth (typically 50 kHz to 200 kHz). The loop bandwidth for PLL2 is chosen to "minimize noise contribution from both PLL and VCO.

Ultra-low jitter is achieved by allowing the phase noise of the external VCXO or crystal to dominate the final output phase noise at low offset frequencies, and thephase noise of the internal VCO to dominate the final output phase noise at high offset frequencies. This results in best overall phase noise and jitter performance.

9.1.2 JEDEC JESD204B Support

The LMK04828-EP provides support for JEDEC JESD204B. The LMK04828-EP will clock up to seven JESD204B targets using seven device clocks (DCLKoutX) and seven SYSREF clocks (SDCLKoutY). Each device clock is grouped with a SYSREF clock.

It is also possible to reprogram SYSREF clocks to behave as extra device clocks for applications which have non-JESD204B clock requirements.

9.1.3 Three PLL1 Redundant Reference Inputs (CLKin0/CLKin0, CLKin1/CLKin1, and CLKin2/CLKin2*)

The LMK04828-EP has up to three reference clock inputs for PLL1: they are CLKin0, CLKin1, and CLKin2. The active clock is chosen based on CLKin_SEL_MODE. Automatic or manual switching can occur between the inputs.

CLKin0, CLKin1, and CLKin2 each have their own PLL1 R dividers.

CLKin1 is shared for use as an external 0-delay feedback (FBCLKin), or for use with an external VCO (Fin).

CLKin2 is shared for use as OSCout. To use power-down OSCout, see VCO_MUX, OSCout_MUX, OSCout_FMT.

Fast manual switching between reference clocks is possible with a external pins CLKin_SEL0 and CLKin_SEL1.

9.1.4 VCXO or Crystal Buffered Output

The LMK04828-EP provides OSCout, which by default is a buffered copy of the PLL1 feedback and PLL2 reference input. This reference input is typically a low noise VCXO or Crystal. When using a VCXO, this output can be used to clock external devices such as microcontrollers, FPGAs, CPLDs, and so forth, before the LMK04828-EP is programmed.

The OSCout buffer output type is programmable to LVDS, LVPECL, or LVCMOS.

The VCXO or Crystal buffered output can be synchronized to the VCO clock distribution outputs by using Cascaded 0-Delay Mode. The buffered output of VCXO/Crystal has deterministic phase relationship with CLKin.

9.1.5 Frequency Holdover

The LMK04828-EP supports holdover operation to keep the clock outputs on frequency with minimum drift when the reference is lost until a valid reference clock signal is re-established.

9.1.6 PLL2 Integrated Loop Filter Poles

The LMK04828-EP features programmable 3rd and 4th order loop filter poles for PLL2. These internal resistors and capacitor values may be selected from a fixed range of values to achieve either a 3rd or 4th order loop filter response. The integrated programmable resistors and capacitors compliment external components mounted near the chip.

These integrated components can be effectively disabled by programming the integrated resistors and capacitors to their minimum values.

9.1.7 Internal VCOs

The LMK04828-EP has two internal VCOs, selected by VCO_MUX. The output of the selected VCO is routed to the Clock Distribution Path. This same selection is also fed back to the PLL2 phase detector through a prescaler and N-divider.

9.1.8 External VCO Mode

The Fin/Fin* input allows an external VCO to be used with PLL2 of the LMK04828-EP.

Using an external VCO reduces the number of available clock inputs by one.

9.1.9 Clock Distribution

The LMK04828-EP features a total of 14 PLL2 clock outputs driven from the internal or external VCO.

All PLL2 clock outputs have programmable output types. They can be programmed to LVPECL, LVDS, or HSDS, or LCPECL.

If OSCout is included in the total number of clock outputs the LMK04828-EP is able to distribute, then up to 15 differential clocks. OSCout may be a buffered version of OSCin, DCLKout6, DCLKout8, or SYSREF.

The following sections discuss specific features of the clock distribution channels that allow the user to control various aspects of the output clocks.

9.1.9.1 Device Clock Divider

Each device clock, DCLKoutX, has a single clock output divider. The divider supports a divide range of 1 to 32 (even and odd) with 50% output duty cycle using duty cycle correction mode. The output of this divider may also be directed to SDCLKoutY, where Y = X + 1.

9.1.9.2 SYSREF Clock Divider

The SYSREF clocks, SDCLKoutY, all share a common divider. The divider supports a divide range of 8 to 8191 (even and odd).

9.1.9.3 Device Clock Delay

The device clocks include both a analog and digital delay for phase adjustment of the clock outputs.

The analog delay allows a nominal 25 ps step size and range from 0 to 575 ps of total delay. Enabling the analog delay adds a nominal 500 ps of delay in addition to the programmed value.

The digital delay allows a group of outputs to be delayed from 4 to 32 VCO cycles. The delay step can be as small as half the period of the clock distribution path. For example, 2-GHz VCO frequency results in 250-ps coarse tuning steps. The coarse (digital) delay value takes effect on the clock outputs after a SYNC event.

There are two different ways to use the digital delay.

Fixed Digital Delay - Allows all the outputs to have a known phase relationship upon a SYNC event. Typically performed at start-up.
Dynamic Digital Delay - Allows the phase relationships of clocks to change while clocks continue to operate.

9.1.9.4 SYSREF Delay

The global SYSREF divider includes a digital delay block which allows a global phase shift with respect to the other clocks.

Each local SYSREF clock output includes both an analog and additional local digital delay for unique phase adjustment of each SYSREF clock.

The local analog delay allows for 150-ps steps.

The local digital delay and SYSREF_HS bit allows the each individual SYSREF output to be delayed from, 1.5 to 11 VCO cycles. The delay step can be as small as half the period of the clock distribution path by using the DCLKoutX_HS bit. For example, 2-GHz VCO frequency results in 250-ps coarse tuning steps.

9.1.9.5 Glitchless Half Step and Glitchless Analog Delay

The device clocks include a features to ensure glitchless operation of the half step and analog delay operations when enabled.

9.1.9.6 Programmable Output Formats

For increased flexibility, all LMK04828-EP device and SYSREF clock outputs (DCLKoutX and SDCLKoutY) can be programmed to an LVDS, HSDS, LVPECL, or LCPECL output type. The OSCout can be programmed to an LVDS, LVPECL, or LVCMOS output type.

Any LVPECL output type can be programmed to 1600-mVpp or 2000-mVpp amplitude levels. The 2000-mVpp LVPECL output type is a Texas Instruments proprietary configuration that produces a 2000-mVpp differential swing for compatibility with many data converters and is also known as 2VPECL.

LCPECL allows for DC-coupling SYSREF to low voltage converters.

9.1.9.7 Clock Output Synchronization

Using the SYNC input causes all active clock outputs to share a rising edge as programmed by fixed digital delay.

The SYNC event must occur for digital delay values to take effect.

9.1.10 0-Delay

The LMK04828-EP supports two types of 0-delay.

Cascaded 0-delay
Nested 0-delay

Cascaded 0-delay mode establishes a fixed deterministic phase relationship of the phase of the PLL2 input clock (OSCin) to the phase of a clock selected by the feedback mux. The 0-delay feedback may performed with an internal feedback from CLKout6, CLKout8, SYSREF, or with an external feedback loop into the FBCLKin port as selected by the FB_MUX. Because OSCin has a fixed deterministic phase relationship to the feedback clock, OSCout will also have a fixed deterministic phase relationship to the feedback clock. In this mode PLL1 input clock (CLKinX) also has a fixed deterministic phase relationship to PLL2 input clock (OSCin), this results in a fixed deterministic phase relationship between all clocks from CLKinX to the clock outputs.

Nested 0-delay mode establishes a fixed deterministic phase relationship of the phase of the PLL1 input clock (CLKinX) to the phase of a clock selected by the feedback mux. The 0-delay feedback may performed with an internal feedback from CLKout6, CLKout8, SYSREF, or with an external feedback loop into the FBCLKin port as selected by the FB_MUX.

Without using 0-delay mode there will be n possible fixed phase relationships from clock input to clock output depending on the clock output divide value.

Using an external 0-delay feedback reduces the number of available clock inputs by one.

9.1.11 Status Pins

The LMK04828-EP provides status pins which can be monitored for feedback or in some cases used for input depending upon device programming. For example:

The CLKin_SEL0 pin may indicate the LOS (loss-of-signal) for CLKin0.
The CLKin_SEL1 pin may be an input for selecting the active clock input.
The Status_LD1 pin may indicate if the device is locked.
The Status_LD2 pin may indicate if PLL2 is locked.

The status pins can be programmed to a variety of other outputs including PLL divider outputs, combined PLL lock detect signals, PLL1 Vtune railing, readback, and so forth. Refer to the programming section of this data sheet for more information.

9.2 Functional Block Diagram

Figure 6 illustrate the complete LMK04828-EP block diagram.

LMK04828-EP LMK04828_detailed_block_diagram.gif

Figure 6. Detailed LMK04828-EP Block Diagram

LMK04828-EP fbd_clksysout_SNAS605_updated020315.gif

Figure 7. Device and SYSREF Clock Output Block

Figure 8. SYNC/SYSREF Clocking Paths

9.3 Feature Description

9.3.1 SYNC/SYSREF

The SYNC and SYSREF signals share the same clocking path. To properly use SYNC or SYSREF for JESD204B, it is important to understand the SYNC and SYSREF system. Figure 7 illustrates the detailed diagram of a clock output block with SYNC circuitry included. Figure 8 illustrates the interconnects and highlights some important registers used in controlling the device for SYNC and SYSREF purposes.

To reset or synchronize a divider, the following conditions must be met:

SYNC_EN must be set. This ensures proper operation of the SYNC circuitry.
SYSREF_MUX and SYNC_MODE must be set to a proper combination to provide a valid SYNC or SYSREF signal.
- If SYSREF block is being used, the SYSREF_PD bit must be clear.
- If the SYSREF Pulser is being used, the SYSREF_PLSR_PD bit must be clear.
- For each SDCLKoutY being used for SYSREF, respective SDCLKoutY_PD bits must be cleared.
SYSREF_DDLY_PD and DCLKoutX_DDLY_PD bits must be clear to power up the digital delay circuitry during SYNC as use requires.
The SYNC_DISX bit must be clear to allow SYNC/SYSREF signal to divider circuit. The SYSREF_MUX register selects the SYNC source which resets the SYSREF and CLKoutX dividers provided the corresponding SYNC_DISX bit is clear.
Other bits which impact the operation of SYNC signal, such as SYNC_1SHOT_EN, may be set as desired.

Table 2 illustrates the some possible combinations of SYSREF_MUX and SYNC_MODE.

Table 2. Some Possible SYNC Configurations

NAME	SYNC_MODE	SYSREF_MUX	OTHER	DESCRIPTION
SYNC Disabled	0	0	CLKin0_OUT_MUX ≠ 0	No SYNC will occur.
Pin or SPI SYNC	1	0	CLKin0_OUT_MUX ≠ 0	Basic SYNC functionality, SYNC pin polarity is selected by SYNC_POL. To achieve SYNC through SPI, toggle the SYNC_POL bit.
Differential input SYNC	0 or 1	0 or 1	CLKin0_OUT_MUX = 0	Differential CLKin0 now operates as SYNC input.
JESD204B Pulser on pin transition	2	2	SYSREF_PULSE_CNT sets pulse count	Produce SYSREF_PULSE_CNT programmed number of pulses on pin transition. SYNC_POL can be used to cause SYNC via SPI.
JESD204B Pulser on SPI programming	3	2	SYSREF_PULSE_CNT sets pulse count	Programming SYSREF_PULSE_CNT register starts sending the number of pulses.
Re-clocked SYNC	1	1	SYSREF operational, SYSREF Divider as required for training frame size.	Allows precise SYNC for n-bit frame training patterns for non-JESD converters such as LM97600.
External SYSREF request	0	2	SYSREF_REQ_EN = 1 Pulser powered up	When SYNC pin is asserted, continuous SYSERF pulses occur. Turning on and off of the pulses is synchronized to prevent runt pulses from occurring on SYSREF.
Continuous SYSREF	X	3	SYSREF_PD = 0 SYSREF_DDLY_PD = 0 SYSREF_PLSR_PD = 1 ⁽¹⁾	Continuous SYSREF signal.
Direct SYSREF distribution	0	0	CLKin0_OUT_MUX = 0 SDCLKoutY_DDLY = 0 (Local sysref DDLY bypassed) SYSREF_DDLY_PD = 1 SYSREF_PLSR_PD = 1 SYSREF_PD = 1.	A direct fan-out of SYSREF with no re-clocking to clock distribution path.

(1) SDCLKoutY_PD = 0 as required per SYSREF output. This applies to any SYNC or SYSREF output on SDCLKoutY when SDCLKoutY_MUX = 1 (SYSREF output)

9.3.2 JEDEC JESD204B

9.3.2.1 How To Enable SYSREF

Table 3 summarizes the bits needed to make SYSREF functionality operational.

Table 3. SYSREF Bits

REGISTER	FIELD	VALUE	DESCRIPTION
0x140	SYSREF_PD	0	Must be clear, power-up SYSREF circuitry.
0x140	SYSREF_DDLY_PD	0	Must be clear to power-up digital delay circuitry during initial SYNC to ensure deterministic timing.
0x143	SYNC_EN	1	Must be set, enable SYNC.
0x143	SYSREF_CLR	1 → 0	Do not hold local SYSREF DDLY block in reset except at start. Anytime SYSREF_PD = 1 because of user programming or device RESET, it is necessary to set SYSREF_CLR for 15 VCO clock cycles to clear the local SYSREF digital delay. Once cleared, SYSREF_CLR must be cleared to allow SYSREF to operate.

Enabling JESD204B operation involves synchronizing all the clock dividers with the SYSREF divder, then configuring the actual SYSREF functionality.

9.3.2.1.1 Setup of SYSREF Example

The following procedure is a programming example for a system which is to operate with a 3000 MHz VCO frequency. Use DCLKout0 and DCLKout2 to drive converters at 1500 MHz. Use DCLKout4 to drive an FPGA at 150 MHz. Synchronize the converters and FPGA using a two SYSREF pulses at 10 MHz.

Program registers 0x000 to 0x1fff as desired, but follow the Recommended Programming Sequence section for out-of-order registers. Key to prepare for SYSREF operations:
1. Prepare for manual SYNC: SYNC_POL = 0, SYNC_MODE = 1, SYSREF_MUX = 0
2. Set up output dividers as per example: DCLKout0_DIV and DCLKout2_DIV = 2 for frequency of 1500 MHz. DCLKout4_DIV = 20 for frequency of 150 MHz.
3. Set up output dividers as per example: SYSREF_DIV = 300 for 10 MHz SYSREF
4. Set up SYSREF: SYSREF_PD = 0, SYSREF_DDLY_PD = 0, DCLKout0_DDLY_PD = 0, DCLKout2_DDLY_PD = 0, DCLKout4_DDLY_PD = 0, SYNC_EN = 1, SYSREF_PLSR_PD = 0, SYSREF_PULSE_CNT = 1 (2 pulses). SDCLKout1_PD = 0, SDCLKout3_PD = 0
5. Clear Local SYSREF DDLY: SYSREF_CLR = 1.
Establish deterministic phase relationships between SYSREF and Device Clock for JESD204B:
1. Set device clock and SYSREF divider digital delays: DCLKout0_DDLY_CNTH, DCLKout0_DDLY_CNTL, DCLKout2_DDLY_CNTH, DCLKout2_DDLY_CNTL, DCLKout4_DDLY_CNTH, DCLKout4_DDLY_CNTL, SYSREF_DDLY.
2. Set device clock digital delay half steps: DCLKout0_HS, DCLKout2_HS, DCLKout4_HS.
3. Set SYSREF clock digital delay as required to achieve known phase relationships: SDCLKout1_DDLY, SDCLKout3_DDLY, SDCLKout5_DDLY.
4. To allow SYNC to affect dividers: SYNC_DIS0 = 0, SYNC_DIS2 = 0, SYNC_DIS4 = 0, SYNC_DISSYSREF = 0
5. Perform SYNC by toggling SYNC_POL = 1 then SYNC_POL = 0.
Disable SYNC from resetting these dividers when the dividers are synchronized. It is not desired for SYSREF to reset the divider of the SYSREF or the dividers of the output clocks.
1. Prevent SYNC (SYSREF) from affecting dividers: SYNC_DIS0 = 1, SYNC_DIS2 = 1, SYNC_DIS4 = 1, SYNC_DISSYSREF = 1.
Release reset of local SYSREF digital delay.
1. SYSREF_CLR = 0. Note this bit needs to be set for only 15 VCO clocks after SYSREF_PD = 0.
Set SYSREF operation.
1. Allow pin SYNC event to start pulser: SYNC_MODE = 2.
2. Select pulser as SYSREF signal: SYSREF_MUX = 2.
Complete! Now asserting the SYNC pin, or toggling SYNC_POL will result in a series of two SYSREF pulses.

9.3.2.1.2 SYSREF_CLR

The local digital delay of the SDCLKout is implemented as a shift buffer. To ensure no unwanted pulses occur at this SYSREF output at start-up, when using SYSREF, users must clear the buffers by setting SYSREF_CLR = 1 for 15 VCO clock cycles. The SYSREF_CLR bit is set after a POR or software reset, so it must be cleared before the SYSREF output is used.

9.3.2.2 SYSREF Modes

9.3.2.2.1 SYSREF Pulser

This mode allows for the output of 1, 2, 4, or 8 SYSREF pulses for every SYNC pin event or SPI programming. This implements the gapped periodic functionality of the JEDEC JESD204B specification.

When in SYSREF Pulser mode, programming the field SYSREF_PULSE_CNT in register 0x13E results in the pulser sending the programmed number of pulses.

9.3.2.2.2 Continuous SYSREF

This mode allows for continuous output of the SYSREF clock.

Continuous operation of SYSREF is not recommended due to crosstalk from the SYSREF clock to device clock. JESD204B is designed to operate with a single burst of pulses to initialize the system at start-up after which it is theoretically not required to send another SYSREF because the system continues to operate with deterministic phases.

If continuous operation of SYSREF is required, consider using a SYSREF output from a non-adjacent output or SYSREF from the OSCout pin to minimize crosstalk.

9.3.2.2.3 SYSREF Request

This mode allows an external source to synchronously turn on or off a continuous stream of SYSREF pulses using pin 6, the SYNC/SYSREF_REQ pin.

Setup the mode by programming SYSREF_REQ_EN = 1 and SYSREF_MUX = 2 (Pulser). The pulser does not need to be powered for this mode of operation.

When the SYSREF_REQ pin is asserted, the SYSREF_MUX will synchronously be set to continuous mode providing continuous pulses at the SYSREF frequency until the SYSREF_REQ pin is un-asserted and the final SYSREF pulse will complete sending synchronously.

9.3.3 Digital Delay

Digital (coarse) delay allows a group of outputs to be delayed by 4 to 32 VCO cycles. The delay step can be as small as half the period of the VCO cycle by using the DCLKoutX_HS bit. There are two different ways to use the digital delay:

Fixed digital delay
Dynamic digital delay

In both delay modes, the regular clock divider is substituted with an alternative divide value. The substitute divide value consists of two values, DCLKoutX_DDLY_CNTH and DCLKoutX_DDLY_CNTL. The minimum _CNTH or _CNTL value is 2 and the maximum _CNTH or _CNTL value is 16. This results in a minimum alternative divide value of 4 and a maximum of 32.

9.3.3.1 Fixed Digital Delay

Fixed digital delay value takes effect on the clock outputs after a SYNC event. As such, the outputs are LOW for a while during the SYNC event. Applications that cannot accept clock breakup when adjusting digital delay should use dynamic digital delay.

9.3.3.1.1 Fixed Digital Delay Example

Assume the device already has the following initial configurations, and the application should delay DCLKout2 by one VCO cycle compared to DCLKout0.

VCO frequency = 2949.12 MHz
DCLKout0 = 368.64 MHz (DCLKout0_DIV = 8)
DCLKout2 = 368.64 MHz (DCLKout2_DIV = 8)

The following steps should be followed

Set DCLKout0_DDLY_CNTH = 4 and DCLKout2_DDLY_CNTH = 4. First part of delay for each clock.
Set DCLKout0_DDLY_CNTL = 4 and DCLKout2_DDLY_CNTL = 5. Second part of delay for each clock.
Set DCLKout0_DDLY_PD = 0 and DCLKout2_DDLY_PD = 0. Power up the digital delay circuit.
Set SYNC_DIS0 = 0 and SYNC_DIS2 = 0. Allow the output to be synchronized.
Perform SYNC by asserting, then unasserting SYNC. Either by using SYNC_POL bit or the SYNC pin.
Now that the SYNC is complete, to save power it is allowable to power down DCLKout0_DDLY_PD = 1 and/or DCLKout2_DDLY_PD = 1.
Set SYNC_DIS0 = 1 and SYNC_DIS2 = 1. To prevent the output from being synchronized, very important for steady state operation when using JESD204B.

Figure 9. Fixed Digital Delay Example

9.3.3.2 Dynamic Digital Delay

Dynamic digital delay allows the phase of clocks to be changed with respect to each other with little impact to the clock signal. This is accomplished by substituting the regular clock divider with an alternate divide value for one cycle. This substitution occurs a number of times equal to the value programmed into the DDLYd_STEP_CNT field for all outputs with DDLYdX_EN = 1 or DDLYd_SYSREF_EN = 1 (see DDLYd_SYSREF_EN, DDLYdX_EN) and DCLKoutX_DDLY_PD = 0 or SYSREF_DDLY_PD = 0.

By programming a larger alternate divider (delay) value, the phase of the adjusted outputs are delayed with respect to the other clocks.
By programming a smaller alternate divider (delay) value, the phase of the adjusted output advances with respect to the other clocks.

NOTE

When programming DDLYd_STEP_CNT to execute more than one step adjustment, the output frequency of the lowest frequency divider having dynamic digital delay enabled must be greater than or equal to 50 MHz to ensure every programmed step is taken. If not, DDLYd_STEP_CNT must be programmed with single step adjustments. When programming back-to-back single DDLYd_STEP_CNT adjustments, wait 70 ns + period of slowest clock for which dynamic digital delay is enabled between DDLYd_STEP_CNT register programmings. This note typically only applies to dynamic digital delay adjustments on the SYSREF divider.

Table 4 shows the recommended DCLKoutX_DDLY_CNTH and DCLKoutX_DDLY_CNTL alternate divide setting for delay by one VCO cycle. The clock outputs high during the DCLKoutX_DDLY_CNTH time to permit a continuous output clock. The clock output is low during the DCLKoutX_DDLY_CNTL time.

When using dynamic digital delay, before the divider SYNC occurs, it is required to setup DCLKoutX_DDLY_CNTH/CNTL and DCLKoutX_DDLYd_CNTH/CNTL values to be the same. After a divider SYNC it is not permitted to change either of these values. If a different phase alignment is required that what is programmed, use the DDLYdX_EN/DDLYd_SYSREF_EN bits to toggle which dividers respond to a dynamic digital delay and execute dynamic digital delay adjustments so outputs have the required phase.

Table 4. Recommended DCLKoutX_DDLY_CNTH/_CNTL and DCLKoutX_DDLYd_CNTH/_CNTL Values for Delay by One VCO Cycle

CLOCK DIVIDER	_CNTH	_CNTL	CLOCK DIVIDER	_CNTH	_CNTL
2	2	3	17	9	9
3	3	4	18	9	10
4	2	3	19	10	10
5	3	3	20	10	11
6	3	4	21	11	11
7	4	4	22	11	12
8	4	5	23	12	12
9	5	5	24	12	13
10	5	6	25	13	13
11	6	6	26	13	14
12	6	7	27	14	14
13	7	7	28	14	15
14	7	8	29	15	15
15	8	8	30	15	16⁽¹⁾
16	8	9	31	16⁽¹⁾	16⁽¹⁾

(1) To achieve _CNTH/_CNTL value of 16, 0 must be programmed into the _CNTH/_CNTL field.

9.3.3.3 Single and Multiple Dynamic Digital Delay Example

In this example, two separate adjustments are made to the device clocks. In the first adjustment, a single delay of one VCO cycle occurs between DCLKout2 and DCLKout0. In the second adjustment, two delays of one VCO cycle occurs between DCLKout2 and DCLKout0. At this point in the example, DCLKout2 is delayed three VCO cycles behind DCLKout0.

Assuming the device already has the following initial configurations and has had the dividers synchronized:

VCO frequency: 2949.12 MHz
DCLKout0 = 368.64 MHz, DCLKout0_DIV = 8
DCLKout2 = 368.64 MHz, DCLKout2_DIV = 8

The following steps illustrate the example above:

1. DCLKout2_DDLY_CNTH = 4 and DCLKout2_DDLYd_CNTH = 4. The delays of DCLKout2 and DCLKout0 are set before divider SYNC. Same settings were used for DLCKout0.

2. DCLKout2_DDLY_CNTL = 5 and DCLKout2_DDLYd_CNTL = 5. The delays of DCLKout2 and DCLKout0 are set before divider SYNC. Same settings were used for DLCKout0. Together with the high count, this gives a substituted divide of 9.

3. Set DCLKout2_DDLY_PD = 0 if not already powered up. This enable the digital delay for DCLKout2. Note it is required for the DDLY_PD = 0 during SYNC to ensure deterministic phase from the SYNC.

4. Set DDLYd2_EN = 1. Enable dynamic digital delay for DCLKout2.

5. Set DDLYd_STEP_CNT = 1. This begins the first adjustment.

Before step 5, DCLKout2 clock edge is aligned with DCLKout0.

After step 5, DCLKout2 counts four VCO cycles high and then five VCO cycles low as programmed by DCLKout2_DDLYd_CNTH and DCLKout2_DDLYd_CNTL fields, effectively delaying DCLKout2 by one VCO cycle with respect to DCLKout0. This is the first adjustment.

6. Set DDLYd_STEP_CNT = 2. This begins the second adjustment.

Before step 6, DCLKout2 clock edge was delayed 1 VCO cycle from DCLKout0.

After step 6, DCLKout2 counts four VCO cycles high and then five VCO cycles low as programmed by DCLKout2_DDLYd_CNTH and DCLKout2_DDLYd_CNTL fields twice, but not necessarily back to back. In total this delays DCLKout2 by two VCO cycles with respect to DCLKout0. This is the second adjustment illustrating multi-step.

Figure 10. Single and Multiple Adjustment Dynamic Digital Delay Example

9.3.4 SYSREF to Device Clock Alignment

To ensure proper JESD204B operation, the timing relationship between the SYSREF and the Device clock must be adjusted for optimum setup and hold time. The ts_JESD204B defines the time between SYSREF and Device Clock for a specific condition of SYSREF divider and Device Clock digital delay. From this point, the SYSREF_DDLY. SDCLKoutY_DDLY, DCLKoutX_DDLY_CNTH, DCLKoutDDLY_CNTL, and DCLKoutX_MUX, SDCKLoutX_ADLY, and so forth. can be adjusted to provide the required setup and hold time between SYSREF and Device Clock.

It is possible to digitally adjust the SYSREF up to 20 VCO cycles before the SYSREF. So for example with a 2949.12 MHz VCO frequency, ts_JESD204B + 20 × (1/VCO Frequency) = –80 ps + 20 × (1/2949.12 MHz) = 6.7 ns.

9.3.5 Input Clock Switching

Manual, pin select, and automatic are three different kinds clock input switching modes can be set with the CLKin_SEL_MODE register.

Below is information about how the active input clock is selected and what causes a switching event in the various clock input selection modes.

9.3.5.1 Input Clock Switching - Manual Mode

When CLKin_SEL_MODE is 0, 1, or 2 then CLKin0, CLKin1, or CLKin2 respectively is always selected as the active input clock. Manual mode also overrides the EN_CLKinX bits such that the CLKinX buffer operates even if CLKinX is disabled with EN_CLKinX = 0.

If holdover is entered in this mode, then the device relocks to the selected CLKin upon holdover exit.

9.3.5.2 Input Clock Switching - Pin Select Mode

When CLKin_SEL_MODE is 3, the pins CLKin_SEL0 and CLKin_SEL1 select which clock input is active.

Configuring Pin Select Mode

The CLKin_SEL0_TYPE must be programmed to an input value for the CLKin_SEL0 pin to function as an input for pin select mode.

The CLKin_SEL1_TYPE must be programmed to an input value for the CLKin_SEL1 pin to function as an input for pin select mode.

If the CLKin_SELX_TYPE is set as output, the pin input value is considered LOW.

The polarity of CLKin_SEL0 and CLKin_SEL1 input pins can be inverted with the CLKin_SEL_INV bit.

Table 5 defines which input clock is active depending on CLKin_SEL0 and CLKin_SEL1 state.

Table 5. Active Clock Input - Pin Select Mode, CLKin_SEL_INV = 0

PIN CLKin_SEL1	PIN CLKin_SEL0	ACTIVE CLOCK
Low	Low	CLKin0
Low	High	CLKin1
High	Low	CLKin2
High	High	Holdover

The pin select mode overrides the EN_CLKinX bits such that the CLKinX buffer operates even if CLKinX is disabled with EN_CLKinX = 0. To switch as fast as possible, the clock input buffers (EN_CLKinX = 1) that could be switched to must remain enabled..

9.3.5.3 Input Clock Switching - Automatic Mode

When CLKin_SEL_MODE is 4, the active clock is selected in round-robin order of enabled clock inputs starting upon an input clock switch event. The switching order of the clocks is CLKin0 → CLKin1 → CLKin2 → CLKin0, and so forth.

For a clock input to be eligible to be switched through, it must be enabled using EN_CLKinX.

Starting Active Clock

Upon programming this mode, the currently active clock remains active if PLL1 lock detect is high. To ensure a particular clock input is the active clock when starting this mode, program CLKin_SEL_MODE to the manual mode which selects the desired clock input (CLKin0, 1, or 2). Wait for PLL1 to lock PLL1_DLD = 1, then select this mode with CLKin_SEL_MODE = 4.

9.3.6 Digital Lock Detect

Both PLL1 and PLL2 support digital lock detect. Digital lock detect compares the phase between the reference path (R) and the feedback path (N) of the PLL. When the time error, which is phase error, between the two signals is less than a specified window size (ε) a lock detect count increments. When the lock detect count reaches a user specified value, PLL1_DLD_CNT or PLL2_DLD_CNT, lock detect is asserted true. Once digital lock detect is true, a single phase comparison outside the specified window causes digital lock detect to be asserted false. This is illustrated in Figure 11.

LMK04828-EP digital_lock_detect_flow_chart.gif

Figure 11. Digital Lock Detect Flowchart

This incremental lock detect count feature functions as a digital filter to ensure that lock detect isn't asserted for only a brief time when the phases of R and N are within the specified tolerance for only a brief time during initial phase lock.

See Digital Lock Detect Frequency Accuracy for more detailed information on programming the registers to achieve a specified frequency accuracy in ppm with lock detect.

The digital lock detect signal can be monitored on the Status_LD1 or Status_LD2 pin. The pin may be programmed to output the status of lock detect for PLL1, PLL2, or both PLL1 and PLL2.

9.3.6.1 Calculating Digital Lock Detect Frequency Accuracy

See Digital Lock Detect Frequency Accuracy for more detailed information on programming the registers to achieve a specified frequency accuracy in ppm with lock detect.

The digital lock detect feature can also be used with holdover to automatically exit holdover mode. See Exiting Holdover for more info.

9.3.7 Holdover

Holdover mode causes PLL2 to stay locked on frequency with minimal frequency drift when an input clock reference to PLL1 becomes invalid. While in holdover mode, the PLL1 charge pump is TRI-STATED and a fixed tuning voltage is set on CPout1 to operate PLL1 in open loop.

9.3.7.1 Enable Holdover

Program HOLDOVER_EN = 1 to enable holdover mode.

Holdover mode can be configured to set the CPout1 voltage upon holdover entry to a fixed user defined voltage or a tracked voltage.

9.3.7.1.1 Fixed (Manual) CPout1 Holdover Mode

By programming MAN_DAC_EN = 1, then the MAN_DAC value is set on the CPout1 pin during holdover.

The user can optionally enable CPout1 voltage tracking (TRACK_EN = 1), read back the tracked DAC value, then re-program MAN_DAC value to a user desired value based on information from previous DAC read backs. This allows the most user control over the holdover CPout1 voltage, but also requires more user intervention.

9.3.7.1.2 Tracked CPout1 Holdover Mode

By programming MAN_DAC_EN = 0 and TRACK_EN = 1, the tracked voltage of CPout1 is set on the CPout1 pin during holdover. When the DAC has acquired the current CPout1 voltage, the DAC_Locked signal is set which may be observed on Status_LD1 or Status_LD2 pins by programming PLL1_LD_MUX or PLL2_LD_MUX respectively.

Updates to the DAC value for the Tracked CPout1 sub-mode occurs at the rate of the PLL1 phase detector frequency divided by (DAC_CLK_MULT × DAC_CLK_CNTR).

The DAC update rate should be programmed for ≤ 100 kHz to ensure DAC holdover accuracy.

The ability to program slow DAC update rates, for example one DAC update per 4.08 seconds when using 1024 kHz PLL1 phase detector frequency with DAC_CLK_MULT = 16,384 and DAC_CLK_CNTR = 255, allows the device to look-back and set CPout1 at previous good CPout1 tuning voltage values before the event which caused holdover to occur.

The current voltage of DAC value can be read back using RB_DAC_VALUE, see RB_DAC_VALUE .

9.3.7.2 During Holdover

PLL1 is run in open loop mode.

PLL1 charge pump is set to TRI-STATE.
PLL1 DLD is un-asserted.
The HOLDOVER status is asserted
During holdover If PLL2 was locked prior to entry of holdover mode, PLL2 DLD continues to be asserted.
CPout1 voltage is set to:
- a voltage set in the MAN_DAC register (MAN_DAC_EN = 1).
- a voltage determined to be the last valid CPout1 voltage (MAN_DAC_EN = 0).
PLL1 attempts to lock with the active clock input.

The HOLDOVER status signal can be monitored on the Status_LD1 or Status_LD2 pin by programming the PLL1_DLD_MUX or PLL2_DLD_MUX register to Holdover Status.

9.3.7.3 Exiting Holdover

Holdover mode can be exited in one of two ways.

Manually, by programming the device from the host.
Automatically, By a clock operating within a specified ppm of the current PLL1 frequency on the active clock input.

9.3.7.4 Holdover Frequency Accuracy and DAC Performance

When in holdover mode, PLL1 runs in open-loop and the DAC sets the CPout1 voltage. If Fixed CPout1 mode is used, then the output of the DAC is a voltage dependant upon the MAN_DAC register. If Tracked CPout1 mode is used, then the output of the DAC is the voltage at the CPout1 pin before holdover mode was entered. When using Tracked mode and MAN_DAC_EN = 1, during holdover the DAC value is loaded with the programmed value in MAN_DAC, not the tracked value.

When in Tracked CPout1 mode, the DAC has a worst case tracking error of ±2 LSBs once PLL1 tuning voltage is acquired. The step size is approximately 3.2 mV, therefore the VCXO frequency error during holdover mode caused by the DAC tracking accuracy is ±6.4 mV × Kv, where Kv is the tuning sensitivity of the VCXO in use. Therefore, the accuracy of the system when in holdover mode in ppm is:

Equation 1. LMK04828-EP 30102359.gif

Example: consider a system with a 19.2-MHz clock input, a 153.6-MHz VCXO with a Kv of 17 kHz/V. The accuracy of the system in holdover in ppm is:

Equation 2. ±0.71 ppm = ±6.4 mV × 17 kHz/V × 1e6 / 153.6 MHz

It is important to account for this frequency error when determining the allowable frequency error window to cause holdover mode to exit.

9.3.7.5 Holdover Mode - Automatic Exit of Holdover

The LMK048xx device can be programmed to automatically exit holdover mode when the accuracy of the frequency on the active clock input achieves a specified accuracy. The programmable variables include PLL1_WND_SIZE and HOLDOVER_DLD_CNT.

See Digital Lock Detect Frequency Accuracy to calculate the register values to cause holdover to automatically exit upon reference signal recovery to within a user specified ppm error of the holdover frequency.

It is possible for the time to exit holdover to vary because the condition for automatic holdover exit is for the reference and feedback signals to have a time/phase error less than a programmable value. Because it is possible for two clock signals to be very close in frequency but not close in phase, it may take a long time for the phases of the clocks to align themselves within the allowable time/phase error before holdover exits.

9.4 Device Functional Modes

The following section describes the settings to enable various modes of operation for the LMK04828-EP. See Figure 7 and Figure 8 for visual diagrams of each mode.

The LMK04828-EP is a flexible device that can be configured for many different use cases. The following simplified block diagrams help show the user the different use cases of the device.

9.4.1 DUAL PLL

Figure 12 illustrates the typical use case of the LMK04828-EP in dual loop mode. In dual loop mode the reference to PLL1 from CLKin0, CLKin1, or CLKin2. An external VCXO or tunable crystal is used to provide feedback for the first PLL and a reference to the second PLL. This first PLL cleans the jitter with the VCXO or low cost tunable crystal by using a narrow loop bandwidth. The VCXO or tunable crystal output may be buffered through the OSCout port. The VCXO or tunable crystal is used as the reference to PLL2 and may be doubled using the frequency doubler. The internal VCO drives up to seven divide/delay blocks which drive up to 14 clock outputs.

Hitless switching and holdover functionality are optionally available when the input reference clock is lost. Holdover works by fixing the tuning voltage of PLL1 to the VCXO or tunable crystal.

It is also possible to use an external VCO in place of the internal VCO of the PLL2. In this case one less CLKin is available as a reference.

Figure 12. Simplified Functional Block Diagram for Dual Loop Mode

Table 6. Dual Loop Mode Register Configuration

FIELD	REGISTER ADDRESS	FUNCTION	VALUE	SELECTED VALUE
PLL1_NCLK_MUX	0x13F	Selects the input to the PLL1 N divider	0	OSCin
PLL2_NCLK_MUX	0x13F	Selects the input to the PLL2 N divider	0	PLL2_P
FB_MUX_EN	0x13F	Enables the Feedback Mux	0	Disabled
FB_MUX	0x13F	Selects the output of the Feedback Mux	X	Don't care because FB_MUX is disabled
OSCin_PD	0x140	Powers down the OSCin port	0	Powered up
CLKin0_OUT_MUX	0x147	Selects where the output of CLKin0 is directed.	2	PLL1
CLKin1_OUT_MUX	0x147	Selects where the output of CLKin1 is directed.	2	PLL1
VCO_MUX	0x138	Selects the VCO 0, 1, or an external VCO	0 or 1	VCO 0 or VCO 1

9.4.2 0-DELAY Dual PLL

Figure 13 illustrates the use case of cascaded 0-delay dual loop mode. This configuration differs from dual loop mode Figure 12 in that the feedback for PLL2 is driven by a clock output instead of the VCO output. Figure 14 illustrates the use case of nested 0-delay dual loop mode. This configuration is similar to the dual PLL in DUAL PLL except that the feedback to the first PLL is driven by a clock output. This causes the clock outputs to have deterministic phase relationship with the clock input. Since all the clock outputs can be synchronized together, all the clock outputs can share the same deterministic phase relationship with the clock input signal. The feedback to PLL1 can be connected internally as shown using CLKout6, CLKout8, SYSREF, or externally using FBCLKin (CLKin1).

It is also possible to use an external VCO in place of the internal VCO of PLL2, but one less CLKin is available as a reference and external 0-delay feedback is not available.

LMK04828-EP fb_simple_dualloop_0dly_cascaded.gif

Figure 13. Simplified Functional Block Diagram for Cascaded 0-delay Dual Loop Mode

Table 7. Cascaded 0-delay Dual Loop Mode Register Configuration

FIELD	REGISTER ADDRESS	FUNCTION	VALUE	SELECTED VALUE
PLL1_NCLK_MUX	0x13F	Selects the input to the PLL1 N divider.	0	OSCin
PLL2_NCLK_MUX	0x13F	Selects the input to the PLL2 N divider	1	Feedback Mux
FB_MUX_EN	0x13F	Enables the Feedback Mux.	1	Feedback Mux Enabled
FB_MUX	0x13F	Selects the output of the Feedback Mux.	0, 1, or 2	Select between DCLKout6, DCLKout8, SYSREF
OSCin_PD	0x140	Powers down the OSCin port.	0	Powered up
CLKin0_OUT_MUX	0x147	Selects where the output of CLKin0 is directed.	0	PLL1
CLKin1_OUT_MUX	0x147	Selects where the output of CLKin1 is directed.	0 or 2	Fin or PLL1
VCO_MUX	0x138	Selects the VCO 0, 1, or an external VCO	0 or 1	VCO 0 or VCO 1

LMK04828-EP fb_simple_dualloop_0dly_nested.gif

Figure 14. Simplified Functional Block Diagram for Nested 0-delay Dual Loop Mode

Table 8 illustrates nested 0-delay mode. This mode is the same as cascaded except the clock out feedback is to PLL1. The CLKin and CLKout have the same deterministic phase relationship but the VCXO's phase is not deterministic to the CLKin or CLKouts.

Table 8. Nested 0-delay Dual Loop Mode Register Configuration

FIELD	REGISTER ADDRESS	FUNCTION	VALUE	SELECTED VALUE
PLL1_NCLK_MUX	0x13F	Selects the input to the PLL1 N divider.	1	Feedback Mux
PLL2_NCLK_MUX	0x13F	Selects the input to the PLL2 N divider	0	PLL2 P
FB_MUX_EN	0x13F	Enables the Feedback Mux.	1	Enabled
FB_MUX	0x13F	Selects the output of the Feedback Mux.	0, 1, or 2	Select between DCLKout6, DCLKout8, SYSREF
OSCin_PD	0x140	Powers down the OSCin port.	0	Powered up
CLKin0_OUT_MUX	0x147	Selects where the output of CLKin0 is directed.	2	PLL1
CLKin1_OUT_MUX	0x147	Selects where the output of CLKin1 is directed.	0 or 2	Fin or PLL1
VCO_MUX	0x138	Selects the VCO 0, 1, or an external VCO	0 or 1	VCO 0 or VCO 1

9.5 Programming

LMK04828-EP devices are programmed using 24-bit registers. Each register consists of a 1-bit command field (R/W), a 2-bit multibyte field (W1, W0), a 13-bit address field (A12 to A0), and an 8-bit data field (D7 to D0). The contents of each register is clocked in MSB first (R/W), and the LSB (D0) last. During programming, the CS* signal is held low. The serial data is clocked in on the rising edge of the SCK signal. After the LSB is clocked in, the CS* signal goes high to latch the contents into the shift register. In general it is recommended to program registers in numeric order, for example 0x000 to 0x1FFF with exceptions as called out in Recommended Programming Sequence, to achieve proper device operation. This does not preclude the users ability to change single registers during operation.. Each register consists of one or more fields which control the device functionality. See electrical characteristics and Figure 1 for timing details.

R/W bit = 0 is for SPI write. R/W bit = 1 is for SPI read.

W1 and W0 shall be written as 0.

9.5.1 Recommended Programming Sequence

Registers are programmed in numeric order with 0x000 being the first and 0x1FFF being the last register programmed. The recommended programming sequence from POR involves:

Program register 0x000 with RESET = 1.
Program registers in numeric order from 0x000 to 0x165. Ensure the following register is programmed as follows:
– 0x145 = 127 (0x7F)
Program register 0x171 to 0xAA and 0x172 to 0x02 as required by OPT_REG_1 and OPT_REG_2.
Program registers 0x17C and 0x17D as required by OPT_REG_1 and OPT_REG_2.
Program registers 0x166 to 0x1FFF.

Program register 0x171, 0x172, 0x17C (OPT_REG_1) and 0x17D (OPT_REG_2) before programming PLL2 in registers: 0x166, 0x167, and 0x168 to optimize PLL2_N and VCO1 phase noise performance over temperature.

9.5.1.1 SPI LOCK

When writing to SPI_LOCK, registers 0x1FFD, 0x1FFE, and 0x1FFF should all always be written sequentially.

9.5.1.2 SYSREF_CLR

When using SYSREF output, SYSREF local digital delay block should be cleared using SYSREF_CLR bit. See SYSREF_CLR for more infoormation.

9.6 Register Maps

9.6.1 Register Map for Device Programming

Table 9 provides the register map for device programming. Any register can be read from the same data address it is written to.

Table 9. LMK04828-EP Register Map

ADDRESS	DATA
[11:0]	7	6	5	4	3	2	1	0
0x000	RESET	0	0	SPI_3WIRE _DIS	0	0	0	0
0x002	0	0	0	0	0	0	0	POWER DOWN
0x003	ID_DEVICE_TYPE
0x004	ID_PROD[15:8]
0x005	ID_PROD[7:0]
0x006	ID_MASKREV
0x00C	ID_VNDR[15:8]
0x00D	ID_VNDR[7:0]
0x100	0	CLKout0_1 _ODL	CLKout0_1 _IDL	DCLKout0_DIV
0x101	DCLKout0_DDLY_CNTH				DCLKout0_DDLY_CNTL
0x102	DCLKout0_DDLYd_CNTH				DCLKout0_DDLYd_CNTL
0x103	DCLKout0_ADLY					DCLKout0_ ADLY_MUX	DCLKout0_MUX
0x104	0	DCLKout0 _HS	SDCLKout1 _MUX	SDCLKout1_DDLY				SDCLKout1 _HS
0x105	0	0	0	SDCLKout1_ ADLY_EN	SDCLKout1_ADLY
0x106	DCLKout0 _ DDLY_PD	DCLKout0 _ HSg_PD	DCLKout0 _ ADLYg_PD	DCLKout0 _ADLY _PD	CLKout0_1 _PD	SDCLKout1_DIS_MODE		SDCLKout1 _PD
0x107	SDCLKout1 _POL	CLKout1_FMT			DCLKout0 _POL	CLKout0_FMT
0x108	0	CLKout2_3 _ODL	CLKout2_3 _IDL	DCLKout2_DIV
0x109	DCLKout2_DDLY_CNTH				DCLKout2_DDLY_CNTL
0x10A	DCLKout2_DDLYd_CNTH				DCLKout2_DDLYd_CNTL
0x10B	DCLKout2_ADLY					DCLKout2_ ADLY_MUX	DCLKout2_MUX
0x10C	0	DCLKout2 _HS	SDCLKout3 _MUX	SDCLKout3_DDLY				SDCLKout3 _HS
0x10D	0	0	0	SDCLKout3 _ ADLY_EN	SDCLKout3_ADLY
0x10E	DCLKout2 _ DDLY_PD	DCLKout2 _ HSg_PD	DCLKout2 _ ADLYg_PD	DCLKout2 _ADLY _PD	CLKout2_3 _PD	SDCLKout3_DIS_MODE		SDCLKout3 _PD
0x10F	SDCLKout3 _POL	CLKout3_FMT			DCLKout2 _POL	CLKout2_FMT
0x110	0	CLKout4_5 _ODL	CLKout4_5 _IDL	DCLKout4_DIV
0x111	DCLKout4_DDLY_CNTH				DCLKout4_DDLY_CNTL
0x112	DCLKout4_DDLYd_CNTH				DCLKout4_DDLYd_CNTL
0x113	DCLKout4_ADLY					DCLKout4_ ADLY_MUX	DCLKout4_MUX
0x114	0	DCLKout4 _HS	SDCLKout5 _MUX	SDCLKout5_DDLY				SDCLKout5 _HS
0x115	0	0	0	SDCLKout5 _ ADLY_EN	SDCLKout5_ADLY
0x116	DCLKout4 _ DDLY_PD	DCLKout4 _ HSg_PD	DCLKout4 _ ADLYg_PD	DCLKout4 _ADLY _PD	CLKout4_5 _PD	SDCLKout5_DIS_MODE		SDCLKout5 _PD
0x117	SDCLKout5 _POL	CLKout5_FMT			DCLKout4 _POL	CLKout4_FMT
0x118	0	CLKout6_7 _ODL	CLKout6_8 _IDL	DCLKout6_DIV
0x119	DCLKout6_DDLY_CNTH				DCLKout6_DDLY_CNTL
0x11A	DCLKout6_DDLYd_CNTH				DCLKout6_DDLYd_CNTL
0x11B	DCLKout6_ADLY					DCLKout6_ ADLY_MUX	DCLKout6_MUX
0x11C	0	DCLKout6 _HS	SDCLKout7 _MUX	SDCLKout7_DDLY				SDCLKout7 _HS
0x11D	0	0	0	SDCLKout7 _ ADLY_EN	SDCLKout7_ADLY
0x11E	DCLKout6 _ DDLY_PD	DCLKout6 _ HSg_PD	DCLKout6 _ ADLYg_PD	DCLKout6 _ADLY _PD	CLKout6_7 _PD	SDCLKout7_DIS_MODE		SDCLKout7 _PD
0x11F	SDCLKout7 _POL	CLKout7 _FMT			DCLKout6 _POL	CLKout6_FMT
0x120	0	CLKout8_9 _ODL	CLKout8_9 _IDL	DCLKout8_DIV
0x121	DCLKout8_DDLY_CNTH				DCLKout8_DDLY_CNTL
0x122	DCLKout8_DDLYd_CNTH				DCLKout8_DDLYd_CNTL
0x123	DCLKout8_ADLY					DCLKout8 _ ADLY_MUX	DCLKout8_MUX
0x124	0	DCLKout8 _HS	SDCLKout9 _MUX	SDCLKout9_DDLY				SDCLKout9 _HS
0x125	0	0	0	SDCLKout9 _ ADLY_EN	SDCLKout9_ADLY
0x126	DCLKout8 _ DDLY_PD	DCLKout8 _ HSg_PD	DCLKout8 _ ADLYg_PD	DCLKout8 _ADLY _PD	CLKout8_9 _PD	SDCLKout9_DIS_MODE		SDCLKout9 _PD
0x127	SDCLKout9 _POL	CLKout9_FMT			DCLKout8 _POL	CLKout8_FMT
0x128	0	CLKout10 _11 _ODL	CLKout10 _11_IDL	DCLKout10_DIV
0x129	DCLKout10_DDLY_CNTH				DCLKout10_DDLY_CNTL
0x12A	DCLKout10_DDLYd_CNTH				DCLKout10_DDLYd_CNTL
0x12B	DCLKout10_ADLY					DCLKout10 _ ADLY_MUX	DCLKout10_MUX
0x12C	0	DCLKout10 _HS	SDCLKout11 _MUX	SDCLKout11_DDLY				SDCLKout11 _HS
0x12D	0	0	0	SDCKLout11 _ ADLY_EN	SDCLKout11_ADLY
0x12E	DCLKout10 _ DDLY_PD	DCLKout10 _ HSg_PD	DLCLKout10 _ ADLYg_PD	DCLKout10 _ ADLY_PD	CLKout10 _11_PD	SDCLKout11_DIS_MODE		SDCLKout11 _PD
0x12F	SDCLKout11 _POL	CLKout11_FMT			DCLKout10 _POL	CLKout10_FMT
0x130	0	CLKout12 _13 _ODL	CLKout12 _13_IDL	DCLKout12_DIV
0x131	DCLKout12_DDLY_CNTH				DCLKout12_DDLY_CNTL
0x132	DCLKout12_DDLYd_CNTH				DCLKout12_DDLYd_CNTL
0x133	DCLKout12_ADLY					DCLKout12_ ADLY_MUX	DCLKout12_MUX
0x134	0	DCLKout12 _HS	SDCLKout13 _MUX	SDCLKout13_DDLY				SDCLKout13 _HS
0x135	0	0	0	SDCLKout13 _ ADLY_EN	SDCLKout13_ADLY
0x136	DCLKout12 _ DDLY_PD	DCLKout12 _ HSg_PD	DCLKout12 _ ADLYg_PD	DCLKout12 _ ADLY_PD	CLKout12 _13_PD	SDCLKout13_DIS_MODE		SDCLKout13 _PD
0x137	SDCLKout13 _POL	CLKout13_FMT			DCLKout12 _POL	CLKout12_FMT
0x138	0	VCO_MUX		OSCout _MUX	OSCout_FMT
0x139	0	0	0	0	0	SYSREF_ CLKin0_MUX	SYSREF_MUX
0x13A	0	0	0	SYSREF_DIV[12:8]
0x13B	SYSREF_DIV[7:0]
0x13C	0	0	0	SYSREF_DDLY[12:8]
0x13D	SYSREF_DDLY[7:0]
0x13E	0	0	0	0	0	0	SYSREF_PULSE_CNT
0x13F	0	0	0	PLL2_NCLK _MUX	PLL1_NCLK _MUX	FB_MUX		FB_MUX _EN
0x140	PLL1_PD	VCO_LDO_PD	VCO_PD	OSCin_PD	SYSREF_GBL _PD	SYSREF_PD	SYSREF _DDLY_PD	SYSREF _PLSR_PD
0x141	DDLYd_ SYSREF_EN	DDLYd12 _EN	DDLYd10 _EN	DDLYd7_EN	DDLYd6_EN	DDLYd4_EN	DDLYd2_EN	DDLYd0_EN
0x142	0	0	0	DDLYd_STEP_CNT
0x143	SYSREF_DDLY _CLR	SYNC_1SHOT _EN	SYNC_POL	SYNC_EN	SYNC_PLL2 _DLD	SYNC_PLL1 _DLD	SYNC_MODE
0x144	SYNC _DISSYSREF	SYNC_DIS12	SYNC_DIS10	SYNC_DIS8	SYNC_DIS6	SYNC_DIS4	SYNC_DIS2	SYNC_DIS0
0x145	0	1	1	1	1	1	1	1
0x146	0	0	CLKin2_EN	CLKin1_EN	CLKin0_EN	CLKin2_TYPE	CLKin1_TYPE	CLKin0_TYPE
0x147	CLKin_SEL _POL	CLKin_SEL_MODE			CLKin1_OUT_MUX		CLKin0_OUT_MUX
0x148	0	0	CLKin_SEL0_MUX			CLKin_SEL0_TYPE
0x149	0	SDIO_RDBK _TYPE	CLKin_SEL1_MUX			CLKin_SEL1_TYPE
0x14A	0	0	RESET_MUX			RESET_TYPE
0x14B	LOS_TIMEOUT		LOS_EN	TRACK_EN	HOLDOVER _ FORCE	MAN_DAC _EN	MAN_DAC[9:8]
0x14C	MAN_DAC[7:0]
0x14D	0	0	DAC_TRIP_LOW
0x14E	DAC_CLK_MULT		DAC_TRIP_HIGH
0x14F	DAC_CLK_CNTR
0x150	0	CLKin _OVERRIDE	0	HOLDOVER _ PLL1_DET	HOLDOVER _LOS _DET	HOLDOVER _VTUNE_DET	HOLDOVER _HITLESS _SWITCH	HOLDOVER _EN
0x151	0	0	HOLDOVER_DLD_CNT[13:8]
0x152	HOLDOVER_DLD_CNT[7:0]
0x153	0	0	CLKin0_R[13:8]
0x154	CLKin0_R[7:0]
0x155	0	0	CLKin1_R[13:8]
0x156	CLKin1_R[7:0]
0x157	0	0	CLKin2_R[13:8]
0x158	CLKin2_R[7:0]
0x159	0	0	PLL1_N[13:8]
0x15A	PLL1_N[7:0]
0x15B	PLL1_WND_SIZE		PLL1 _CP_TRI	PLL1 _CP_POL	PLL1_CP_GAIN
0x15C	0	0	PLL1_DLD_CNT[13:8]
0x15D	PLL1_DLD_CNT[7:0]
0x15E	0	0	PLL1_R_DLY			PLL1_N_DLY
0x15F	PLL1_LD_MUX					PLL1_LD_TYPE
0x160	0	0	0	0	PLL2_R[11:8]
0x161	PLL2_R[7:0]
0x162	PLL2_P			OSCin_FREQ			PLL2 _XTAL_EN	PLL2 _REF_2X_EN
0x163	0	0	0	0	0	0	PLL2_N_CAL[17:16]
0x164	PLL2_N_CAL[15:8]
0x165	PLL2_N_CAL[7:0]
0x166	0	0	0	0	0	PLL2_FCAL _DIS	PLL2_N[17:16]
0x167	PLL2_N[15:8]
0x168	PLL2_N[7:0]
0x169	0	PLL2_WND_SIZE		PLL2_CP_GAIN		PLL2 _CP_POL	PLL 2_CP_TRI	1
0x16A	0	SYSREF_REQ_EN	PLL2_DLD_CNT[15:8]
0x16B	PLL2_DLD_CNT[7:0]
0x16C	0	0	PLL2_LF_R4			PLL2_LF_R3
0x16D	PLL2_LF_C4				PLL2_LF_C3
0x16E	PLL2_LD_MUX					PLL2_LD_TYPE
0x171	1	0	1	0	1	0	1	0
0x172	0	0	0	0	0	0	1	0
0x173	0	PLL2_PRE_PD	PLL2_PD	0	0	0	0	0
0x174	0	0	0	VCO1_DIV
0x17C	OPT_REG_1
0x17D	OPT_REG_2
0x182	0	0	0	0	0	RB_PLL1_ LD_LOST	RB_PLL1_LD	CLR_PLL1_ LD_LOST
0x183	0	0	0	0	0	RB_PLL2_ LD_LOST	RB_PLL2_LD	CLR_PLL2_ LD_LOST
0x184	RB_DAC_VALUE[9:8]		RB_CLKin2_ SEL	RB_CLKin1_ SEL	RB_CLKin0_ SEL	X	RB_CLKin1_ LOS	RB_CLKin0_ LOS
0x185	RB_DAC_VALUE[7:0]
0x188	0	0	0	RB_ HOLDOVER	X	X	X	X
0x1FFD	SPI_LOCK[23:16]
0x1FFE	SPI_LOCK[15:8]
0x1FFF	SPI_LOCK[7:0]

9.7 Device Register Descriptions

The following section details the fields of each register, the Power On Reset Defaults, and specific descriptions of each bit.

In some cases similar fields are located in multiple registers. In this case specific outputs may be designated as X or Y. In these cases, the X represents even numbers from 0 to 12 and the Y represents odd numbers from 1 to 13. In the case where X and Y are both used in a bit name, then Y = X + 1.

9.7.1 System Functions

9.7.1.1 RESET, SPI_3WIRE_DIS

This register contains the RESET function.

Table 10. Register 0x000

BIT	NAME	POR DEFAULT	DESCRIPTION
7	RESET	0	0: Normal Operation 1: Reset (automatically cleared)
6:5	NA	0	Reserved
4	SPI_3WIRE_DIS	0	Disable 3 wire SPI mode. 4 Wire SPI mode is enabled by selecting SPI Read back in one of the output MUX settings. For example CLKin0_SEL_MUX. 0: 3 Wire Mode enabled 1: 3 Wire Mode disabled
3:0	NA	NA	Reserved

9.7.1.2 POWERDOWN

This register contains the POWERDOWN function.

Table 11. Register 0x002

BIT	NAME	POR DEFAULT	DESCRIPTION
7:1	NA	0	Reserved
0	POWERDOWN	0	0: Normal Operation 1: Powerdown

9.7.1.3 ID_DEVICE_TYPE

This register contains the product device type. This is read only register.

Table 12. Register 0x003

BIT	NAME	POR DEFAULT	DESCRIPTION
7:0	ID_DEVICE_TYPE	6	PLL product device type.

9.7.1.4 ID_PROD[15:8], ID_PROD

These registers contain the product identifier. This is a read only register.

Table 13. ID_PROD Register Configuration, ID_PROD[15:0]

MSB	LSB
0x004[7:0]	0x005[7:0]

BIT	REGISTERS	FIELD NAME	POR DEFAULT	DESCRIPTION
7:0	0x004	ID_PROD[15:8]	208	MSB of the product identifier.
7:0	0x005	ID_PROD	91	LSB of the product identifier.

9.7.1.5 ID_MASKREV

This register contains the IC version identifier. This is a read only register.

Table 14. Register 0x006

BIT	NAME	POR DEFAULT	DESCRIPTION
7:0	ID_MASKREV	32	IC version identifier for LMK04828-EP

9.7.1.6 ID_VNDR[15:8], ID_VNDR

These registers contain the vendor identifier. This is a read only register.

Table 15. ID_VNDR Register Configuration, ID_VNDR[15:0]

MSB	LSB
0x00C[7:0]	0x00D[7:0]

Table 16. Registers 0x00C, 0x00D

BIT	REGISTERS	NAME	POR DEFAULT	DESCRIPTION
7:0	0x00C	ID_VNDR[15:8]	81	MSB of the vendor identifier.
7:0	0x00D	ID_VNDR	4	LSB of the vendor identifier.

9.7.2 (0x100 - 0x138) Device Clock and SYSREF Clock Output Controls

9.7.2.1 CLKoutX_Y_ODL, CLKoutX_Y_IDL, DCLKoutX_DIV

These registers control the input and output drive level as well as the device clock out divider values.

Table 17. Registers 0x100, 0x108, 0x110, 0x118, 0x120, 0x128, and 0x130

BIT	NAME	POR DEFAULT	DESCRIPTION
7	NA	0	Reserved
6	CLKoutX_Y_ODL	0	Output drive level.
5	CLKoutX_Y_IDL	0	Input drive level.
4:0	DCLKoutX_DIV	X = 0 → 2 X = 2 → 4 X = 4 → 8 X = 6 → 8 X = 8 → 8 X = 10 → 8 X = 12 → 2	DCLKoutX_DIV sets the divide value for the clock output, the divide may be even or odd. Both even or odd divides output a 50% duty cycle clock if duty cycle correction (DCC) is selected. Divider is unused if DCLKoutX_MUX = 2 (bypass), equivalent divide of 1.
			Field Value	Divider Value
			0 (0x00)	32
			1 (0x01)	1 ⁽¹⁾
			2 (0x02)	2
			...	...
			30 (0x1E)	30
			31 (0x1F)	31

(1) Not valid if DCLKoutX_MUX = 0, Divider only. Not valid if DCLKoutX_MUX = 3 (Analog Delay + Divider) and DCLKoutX_ADLY_MUX = 0 (without duty cycle correction/halfstep).

9.7.2.2 DCLKoutX_DDLY_CNTH, DCLKoutX_DDLY_CNTL

This register controls the digital delay high and low count values for the device clock outputs.

Table 18. Registers 0x101, 0x109, 0x111, 0x119, 0x121, 0x129, 0x131

BIT	NAME	POR DEFAULT	DESCRIPTION
7:4	DCLKoutX _DDLY_CNTH	5	Number of clock cycles the output will be high when digital delay is engaged.
			Field Value	Delay Values
			0 (0x00)	16
			1 (0x01)	Reserved
			2 (0x02)	2
			...	...
			15 (0x0F)	15
3:0	DCLKoutX _DDLY_CNTL	5	Number of clock cycles the output will be low when digital delay is engaged.
			Field Value	Delay Values
			0 (0x00)	16
			1 (0x01)	Reserved
			2 (0x02)	2
			...	...
			15 (0x0F)	15

9.7.2.3 DCLKoutX_DDLYd_CNTH, DCLKoutX_DDLYd_CNTL

This register controls the digital delay high and low count values for the device clock outputs during dynamic digital delay. The corresponding DCLKoutX_DDLY_CNTH/CNTL registers must be programmed to the same value.

Table 19. Registers 0x102, 0x10A, 0x112, 0x11A, 0x122, 0x12A, 0x132

BIT	NAME	POR DEFAULT	DESCRIPTION
7:4	DCLKoutX _DDLYd_CNTH	5	Number of clock cycles the output will be high when dynamic digital delay is engaged.
			Field Value	Delay Values
			0 (0x00)	16
			1 (0x01)	Reserved
			2 (0x02)	2
			...	...
			15 (0x0F)	15
3:0	DCLKoutX _DDLYd_CNTL	5	Number of clock cycles the output will be low when dynamic digital delay is engaged.
			Field Value	Delay Values
			0 (0x00)	16
			1 (0x01)	Reserved
			2 (0x02)	2
			...	...
			15 (0x0F)	15

9.7.2.4 DCLKoutX_ADLY, DCLKoutX_ADLY_MUX, DCLKout_MUX

These registers control the analog delay properties for the device clocks.

Table 20. Registers 0x103, 0x10B, 0x113, 0x11B, 0x123, 0x12B, 0x133

BIT	NAME	POR DEFAULT	DESCRIPTION
7:3	DCLKoutX_ADLY	0	Device clock analog delay value. Setting this value results in a 500 ps timing delay in additional to the delay of each 25 ps step. Effective range is 500 ps to 1075 ps.
			Field Value	Delay Value
			0 (0x00)	0 ps
			1 (0x01)	25 ps
			2 (0x02)	50 ps
			...	...
			23 (0x17)	575 ps
2	DCLKoutX_ADLY _MUX	0	This register selects the input to the analog delay for the device clock. Used when DCLKoutX_MUX = 3. 0: Divided without duty cycle correction or half step. ⁽¹⁾ 1: Divided with duty cycle correction and half step.
1:0	DCLKoutX_MUX	0	This selects the input to the device clock buffer.
			Field Value	Mux Output
			0 (0x0)	Divider only ⁽¹⁾
			1 (0x1)	Divider with Duty Cycle Correction and Half Step
			2 (0x2)	Bypass
			3 (0x3)	Analog Delay + Divider

(1) DCLKoutX_DIV = 1 is not valid.

9.7.2.5 DCLKoutX_HS, SDCLKoutY_MUX, SDCLKoutY_DDLY, SDCLKoutY_HS

These registers set the half step for the device clock, the SYSREF output MUX, the SYSREF clock digital delay, and half step.

Table 21. Registers 0x104, 0x10C, 0x114, 0x11C, 0x124, 0x12C, 0x134

BIT	NAME	POR DEFAULT	DESCRIPTION
7	NA	0	Reserved
6	DCLKoutX_HS	0	Sets the device clock half step value. Half step must be zero (0) for a divide of 1. 0: 0 cycles 1: -0.5 cycles
5	SDCLKoutY_MUX	0	Sets the input the the SDCLKoutY outputs. 0: Device clock output 1: SYSREF output
4:1	SDCLKoutY_DDLY	0	Sets the number of VCO cycles to delay the SDCLKoutY by when SYSREF output is selected by SDCLKoutY_MUX.
			Field Value	Delay Cycles
			0 (0x00)	Bypass
			1 (0x01)	2
			2 (0x02)	3
			...	...
			10 (0x0A)	11
			11 to 15 (0x0B to 0x0F)	Reserved
0	SDCLKoutY_HS	0	Sets the SYSREF clock half step value. 0: 0 cycles 1: -0.5 cycles

9.7.2.6 SDCLKoutY_ADLY_EN, SDCLKoutY_ADLY

These registers set the analog delay parameters for the SYSREF outputs.

Table 22. Registers 0x105, 0x10D, 0x115, 0x11D, 0x125, 0x12D, 0x135

BIT	NAME	POR DEFAULT	DESCRIPTION
7:5	NA	0	Reserved
4	SDCLKoutY _ADLY_EN	0	Enables analog delay for the SYSREF output. 0: Disabled 1: Enabled
3:0	SDCLKoutY _ADLY	0	Sets the analog delay value for the SYSREF output. Selecting analog delay adds an additional 700 ps in propagation delay. Effective range is 700 ps to 2950 ps.
			Field Value	Delay Value
			0 (0x0)	0 ps
			1 (0x1)	600 ps
			2 (0x2)	750 ps (+150 ps from 0x1)
			3 (0x3)	900 ps (+150 ps from 0x2)
			...	...
			14 (0xE)	2100 ps (+150 ps from 0xD)
			15 (0xF)	2250 ps (+150 ps from 0xE)

9.7.2.7 DCLKoutX_DDLY_PD, DCLKoutX_HSg_PD, DCLKout_ADLYg_PD, DCLKout_ADLY_PD, DCLKoutX_Y_PD, SDCLKoutY_DIS_MODE, SDCLKoutY_PD

This register controls the power down functions for the digital delay, glitchless half step, glitchless analog delay, analog delay, outputs, and SYSREF disable modes.

Table 23. Registers 0x106, 0x10E, 0x116, 0x11E, 0x126, 0x12E, 0x136

BIT	NAME	POR DEFAULT	DESCRIPTION
7	DCLKoutX _DDLY_PD	0	Powerdown the device clock digital delay circuitry. 0: Enabled 1: Powerdown
6	DCLKoutX _HSg_PD	1	Powerdown the device clock glitchless half step feature. 0: Enabled 1: Powerdown
5	DCLKoutX _ADLYg_PD	1	Powerdown the device clock glitchless analog delay feature. 0: Enabled, analog delay step size of one code is glitchless between values 1 to 23. 1: Powerdown
4	DCLKoutX _ADLY_PD	1	Powerdown the device clock analog delay feature. 0: Enabled 1: Powerdown
3	CLKoutX_Y_PD	X_Y = 0_1 → 1 X_Y = 2_3 → 1 X_Y = 4_5 → 0 X_Y = 6_7 → 0 X_Y = 8_9 → 0 X_Y = 10_11 → 0 X_Y = 12_13 → 1	Powerdown the clock group defined by X and Y. 0: Enabled 1: Powerdown
2:1	SDCLKoutY _DIS_MODE	0	Configures the output state of the SYSREF
			Field Value	Disable Mode
			0 (0x00)	Active in normal operation
			1 (0x01)	If SYSREF_GBL_PD = 1, the output is a logic low, otherwise it is active.
			2 (0x02)	If SYSREF_GBL_PD = 1, the output is a nominal Vcm voltage⁽¹⁾, otherwise it is active.
			3 (0x03)	Output is a nominal Vcm voltage⁽¹⁾
0	SDCLKoutY_PD	1	Powerdown SDCLKoutY and set to the state defined by SDCLKoutY_DIS_MODE

(1) If LVPECL mode is used with emitter resistors to ground, the output Vcm will be ~0 V, each pin will be ~0 V.

9.7.2.8 SDCLKoutY_POL, SDCLKoutY_FMT, DCLKoutX_POL, DCLKoutX_FMT

These registers configure the output polarity, and format.

Table 24. Registers 0x107, 0x10F, 0x117, 0x11F, 0x127, 0x12F, 0x137

BIT	NAME	POR DEFAULT	DESCRIPTION
7	SDCLKoutY_POL	0	Sets the polarity of clock on SDCLKoutY when device clock output is selected with SDCLKoutY_MUX. 0: Normal 1: Inverted
6:4	SDCLKoutY_FMT	0	Sets the output format of the SYSREF clocks
			Field Value	Output Format
			0 (0x00)	Powerdown
			1 (0x01)	LVDS
			2 (0x02)	HSDS 6 mA
			3 (0x03)	HSDS 8 mA
			4 (0x04)	HSDS 10 mA
			5 (0x05)	LVPECL 1600 mV
			6 (0x06)	LVPECL 2000 mV
			7 (0x07)	LCPECL
3	DCLKoutX_POL	0	Sets the polarity of the device clocks from the DCLKoutX outputs 0: Normal 1: Inverted
2:0	DCLKoutX_FMT	LMK04828-EP: X = 0 → 0 X = 2 → 0 X = 4 → 1 X = 6 → 1 X = 8 → 1 X = 10 → 1 X = 12 → 0	Sets the output format of the device clocks.
			Field Value	Output Format
			0 (0x00)	Powerdown
			1 (0x01)	LVDS
			2 (0x02)	HSDS 6 mA
			3 (0x03)	HSDS 8 mA
			4 (0x04)	HSDS 10 mA
			5 (0x05)	LVPECL 1600 mV
			6 (0x06)	LVPECL 2000 mV
			7 (0x07)	LCPECL

9.7.3 SYSREF, SYNC, and Device Config

9.7.3.1 VCO_MUX, OSCout_MUX, OSCout_FMT

This register selects the clock distribution source, and OSCout parameters.

Table 25. Register 0x138

BIT	NAME	POR DEFAULT	DESCRIPTION
7	NA	0	Reserved
6:5	VCO_MUX	0	Selects clock distribution path source from VCO0, VCO1, or CLKin (external VCO)
			Field Value	VCO Selected
			0 (0x00)	VCO 0
			1 (0x01)	VCO 1
			2 (0x02)	CLKin1 (external VCO)
			3 (0x03)	Reserved
4	OSCout_MUX	0	Select the source for OSCout: 0: Buffered OSCin 1: Feedback Mux
3:0	OSCout_FMT	4	Selects the output format of OSCout. When powered down, these pins may be used as CLKin2.
			Field Value	OSCout Format
			0 (0x00)	Powerdown (CLKin2)
			1 (0x01)	LVDS
			2 (0x02)	Reserved
			3 (0x03)	Reserved
			4 (0x04)	LVPECL 1600 mVpp
			5 (0x05)	LVPECL 2000 mVpp
			6 (0x06)	LVCMOS (Norm / Inv)
			7 (0x07)	LVCMOS (Inv / Norm)
			8 (0x08)	LVCMOS (Norm / Norm)
			9 (0x09)	LVCMOS (Inv / Inv)
			10 (0x0A)	LVCMOS (Off / Norm)
			11 (0x0B)	LVCMOS (Off / Inv)
			12 (0x0C)	LVCMOS (Norm / Off)
			13 (0x0D)	LVCMOS (Inv / Off)
			14 (0x0E)	LVCMOS (Off / Off)

9.7.3.2 SYSREF_CLKin0_MUX, SYSREF_MUX

This register sets the source for the SYSREF outputs. Refer to Figure 8 and SYNC/SYSREF.

Table 26. Register 0x139

BIT	NAME	POR DEFAULT	DESCRIPTION
7:3	NA	0	Reserved
2	SYSREF_ CLKin0_MUX	0	Selects the SYSREF output from SYSREF_MUX or CLKin0 direct
			Field Value	SYSREF Source
			0	SYSREF Mux
			1	CLKin0 Direct (from CLKin0_OUT_MUX)
1:0	SYSREF_MUX	0	Selects the SYSREF source.
			Field Value	SYSREF Source
			0 (0x00)	Normal SYNC
			1 (0x01)	Re-clocked
			2 (0x02)	SYSREF Pulser
			3 (0x03)	SYSREF Continuous

9.7.3.3 SYSREF_DIV[12:8], SYSREF_DIV[7:0]

These registers set the value of the SYSREF output divider.

Table 27. Registers 0x13A, 0x13B

MSB	LSB
0x13A[4:0]	0x13B[7:0]

BIT	REGISTERS	NAME	POR DEFAULT	DESCRIPTION
7:5	0x13A	NA	0	Reserved
4:0	0x13A	SYSREF_DIV[12:8]	12	Divide value for the SYSREF outputs.
				Field Value	Divide Value
				0x00 to 0x07	Reserved
				8 (0x08)	8
7:0	0x13B	SYSREF_DIV[7:0]	0	9 (0x09)	9
				...	...
				8190 (0x1FFE)	8190
				8191 (0X1FFF)	8191

9.7.3.4 SYSREF_DDLY[12:8], SYSREF_DDLY[7:0]

These registers set the delay of the SYSREF digital delay value.

Table 28. SYSREF Digital Delay Register Configuration, SYSREF_DDLY[12:0]

MSB	LSB
0x13C[4:0]	0x13D[7:0]

BIT	REGISTERS	NAME	POR DEFAULT	DESCRIPTION
7:5	0x13C	NA	0	Reserved
4:0	0x13C	SYSREF_DDLY[12:8]	0	Sets the value of the SYSREF digital delay.
				Field Value	Delay Value
				0x00 to 0x07	Reserved
				8 (0x08)	8
7:0	0x13D	SYSREF_DDLY[7:0]	8	9 (0x09)	9
				...	...
				8190 (0x1FFE)	8190
				8191 (0X1FFF)	8191

9.7.3.5 SYSREF_PULSE_CNT

This register sets the number of SYSREF pulses if SYSREF is not in continuous mode. See SYSREF_CLKin0_MUX, SYSREF_MUX for further description of SYSREF's outputs.

Programming the register causes the specified number of pulses to be output if "SYSREF Pulses" is selected by SYSREF_MUX and SYSREF functionality is powered up.

Table 29. Register 0x13E

BIT	NAME	POR DEFAULT	DESCRIPTION
7:2	NA	0	Reserved
1:0	SYSREF_PULSE_CNT	3	Sets the number of SYSREF pulses generated when not in continuous mode. See SYSREF_CLKin0_MUX, SYSREF_MUX for more information on SYSREF modes.
			Field Value	Number of Pulses
			0 (0x00)	1 pulse
			1 (0x01)	2 pulses
			2 (0x02)	4 pulses
			3 (0x03)	8 pulses

9.7.3.6 PLL2_NCLK_MUX, PLL1_NCLK_MUX, FB_MUX, FB_MUX_EN

This register controls the feedback feature.

Table 30. Register 0x13F

BIT	NAME	POR DEFAULT	DESCRIPTION
7:5	NA	0	Reserved
4	PLL2_NCLK_MUX	0	Selects the input to the PLL2 N Divider 0: PLL Prescaler 1: Feedback Mux
3	PLL1_NCLK_MUX	0	Selects the input to the PLL1 N Delay. 0: OSCin 1: Feedback Mux
2:1	FB_MUX	0	When in 0-delay mode, the feedback mux selects the clock output to be fed back into the PLL1 N Divider.
			Field Value	Source
			0 (0x00)	DCLKout6
			1 (0x01)	DCLKout8
			2 (0x02)	SYSREF Divider
			3 (0x03)	External
0	FB_MUX_EN	0	When using 0-delay, FB_MUX_EN must be set to 1 power up the feedback mux. 0: Feedback mux powered down 1: Feedback mux enabled

9.7.3.7 PLL1_PD, VCO_LDO_PD, VCO_PD, OSCin_PD, SYSREF_GBL_PD, SYSREF_PD, SYSREF_DDLY_PD, SYSREF_PLSR_PD

This register contains powerdown controls for OSCin and SYSREF functions.

Table 31. Register 0x140

BIT	NAME	POR DEFAULT	DESCRIPTION
7	PLL1_PD	0	Powerdown PLL1 0: Normal operation 1: Powerdown
6	VCO_LDO_PD	0	Powerdown VCO_LDO 0: Normal operation 1: Powerdown
5	VCO_PD	0	Powerdown VCO 0: Normal operation 1: Powerdown
4	OSCin_PD	0	Powerdown the OSCin port. 0: Normal operation 1: Powerdown
3	SYSREF_GBL_PD	0	Powerdown individual SYSREF outputs depending on the setting of SDCLKoutY_DIS_MODE for each SYSREF output. SYSREF_GBL_PD allows many SYSREF outputs to be controlled through a single bit. 0: Normal operation 1: Activate Powerdown Mode
2	SYSREF_PD	1	Powerdown the SYSREF circuitry and divider. If powered down, SYSREF output mode cannot be used. SYNC cannot be provided either. 0: SYSREF can be used as programmed by individual SYSREF output registers. 1: Powerdown
1	SYSREF_DDLY_PD	1	Powerdown the SYSREF digital delay circuitry. 0: Normal operation, SYSREF digital delay may be used. Must be powered up during SYNC for deterministic phase relationship with other clocks. 1: Powerdown
0	SYSREF_PLSR_PD	1	Powerdown the SYSREF pulse generator. 0: Normal operation 1: Powerdown

9.7.3.8 DDLYd_SYSREF_EN, DDLYdX_EN

This register enables dynamic digital delay for enabled device clocks and SYSREF when DDLYd_STEP_CNT is programmed.

Table 32. Register 0x141

BIT	NAME	DESCRIPTION
7	DDLYd_SYSREF_EN	Enables dynamic digital delay on SYSREF outputs	0: Disabled 1: Enabled
6	DDLYd12_EN	Enables dynamic digital delay on DCLKout12
5	DDLYd10_EN	Enables dynamic digital delay on DCLKout10
4	DDLYd8_EN	Enables dynamic digital delay on DCLKout8
3	DDLYd6_EN	Enables dynamic digital delay on DCLKout6
2	DDLYd4_EN	Enables dynamic digital delay on DCLKout4
1	DDLYd2_EN	Enables dynamic digital delay on DCLKout2
0	DDLYd0_EN	Enables dynamic digital delay on DCLKout0

9.7.3.9 DDLYd_STEP_CNT

This register sets the number of dynamic digital delay adjustments occur. Upon programming, the dynamic digital delay adjustment begins for each clock output with dynamic digital delay enabled. Dynamic digital delay can only be started by SPI.

Other registers must be set: SYNC_MODE = 3

Table 33. Register 0x142

BIT	NAME	POR DEFAULT	DESCRIPTION
7:4	NA	0	Reserved
3:0	DDLYd_STEP_CNT	0	Sets the number of dynamic digital delay adjustments that will occur.
			Field Value	SYNC Generation
			0 (0x00)	No Adjust
			1 (0x01)	1 step
			2 (0x02)	2 steps
			3 (0x03)	3 steps
			...	...
			14 (0x0E)	14 steps
			15 (0x0F)	15 steps

9.7.3.10 SYSREF_CLR, SYNC_1SHOT_EN, SYNC_POL, SYNC_EN, SYNC_PLL2_DLD, SYNC_PLL1_DLD, SYNC_MODE

This register sets general SYNC parameters such as polarization, and mode. Refer to Figure 8 for block diagram. Refer to Table 2 for using SYNC_MODE for specific SYNC use cases.

Table 34. Register 0x143

BIT	NAME	POR DEFAULT	DESCRIPTION
7	SYSREF_CLR	1	Except during SYSREF Setup Procedure (see SYNC/SYSREF), this bit should always be programmed to 0. While this bit is set, extra current is used. Refer to Table 85.
6	SYNC_1SHOT_EN	0	SYNC one shot enables edge sensitive SYNC. 0: SYNC is level sensitive and outputs will be held in SYNC as long as SYNC is asserted. 1: SYNC is edge sensitive, outputs will be SYNCed on rising edge of SYNC. This results in the clock being held in SYNC for a minimum amount of time.
5	SYNC_POL	0	Sets the polarity of the SYNC pin. 0: Normal 1: Inverted
4	SYNC_EN	1	Enables the SYNC functionality. 0: Disabled 1: Enabled
3	SYNC_PLL2_DLD	0	0: Off 1: Assert SYNC until PLL2 DLD = 1
2	SYNC_PLL1_DLD	0	0: Off 1: Assert SYNC until PLL1 DLD = 1
1:0	SYNC_MODE	1	Sets the method of generating a SYNC event.
			Field Value	SYNC Generation
			0 (0x00)	Prevent SYNC Pin, SYNC_PLL1_DLD flag, or SYNC_PLL2_DLD flag from generating a SYNC event.
			1 (0x01)	SYNC event generated from SYNC pin or if enabled the SYNC_PLL1_DLD flag or SYNC_PLL2_DLD flag.
			2 (0x02)	For use with pulser - SYNC/SYSREF pulses are generated by pulser block via SYNC Pin or if enabled SYNC_PLL1_DLD flag or SYNC_PLL2_DLD flag.
			3 (0x03)	For use with pulser - SYNC/SYSREF pulses are generated by pulser block when programming register 0x13E (SYSREF_PULSE_CNT) is written to (see ).

9.7.3.11 SYNC_DISSYSREF, SYNC_DISX

SYNC_DISX will prevent a clock output from being synchronized or interrupted by a SYNC event or when outputting SYSREF.

Table 35. Register 0x144

BIT	NAME	DESCRIPTION
7	SYNC_DISSYSREF	Prevent the SYSREF clocks from becoming synchronized during a SYNC event. If SYNC_DISSYSREF is enabled it will continue to operate normally during a SYNC event.
6	SYNC_DIS12	Prevent the device clock output from becoming synchronized during a SYNC event or SYSREF clock. If SYNC_DIS bit for a particular output is enabled then it will continue to operate normally during a SYNC event or SYSREF clock.
5	SYNC_DIS10
4	SYNC_DIS8
3	SYNC_DIS6
2	SYNC_DIS4
1	SYNC_DIS2
0	SYNC_DIS0

9.7.3.12 Fixed Register

Always program this register to value 127.

Table 36. Register 0x145

BIT	NAME	POR DEFAULT	DESCRIPTION
7:0	Fixed Register	0	Always program to 127

9.7.4 (0x146 - 0x149) CLKin Control

9.7.4.1 CLKin2_EN, CLKin1_EN, CLKin0_EN, CLKin2_TYPE, CLKin1_TYPE, CLKin0_TYPE

This register has CLKin enable and type controls.

Table 37. Register 0x146

BIT	NAME	POR DEFAULT	DESCRIPTION
7:6	NA	0	Reserved
5	CLKin2_EN	0	Enable CLKin2 to be used during auto-switching of CLKin_SEL_MODE. 0: Not enabled for auto mode 1: Enabled for auto mode
4	CLKin1_EN	1	Enable CLKin1 to be used during auto-switching of CLKin_SEL_MODE. 0: Not enabled for auto mode 1: Enabled for auto mode
3	CLKin0_EN	1	Enable CLKin0 to be used during auto-switching of CLKin_SEL_MODE. 0: Not enabled for auto mode 1: Enabled for auto mode
2	CLKin2_TYPE	0	0: Bipolar 1: MOS	There are two buffer types for CLKin0, 1, and 2: bipolar and CMOS. Bipolar is recommended for differential inputs like LVDS or LVPECL. CMOS is recommended for DC-coupled, single-ended inputs. When using bipolar, CLKinX and CLKinX* must be AC-coupled. When using CMOS, CLKinX and CLKinX* may be AC- or DC-coupled if the input signal is differential. If the input signal is single-ended the used input may be either AC- or DC-coupled and the unused input must AC grounded.
1	CLKin1_TYPE	0
0	CLKin0_TYPE	0

9.7.4.2 CLKin_SEL_POL, CLKin_SEL_MODE, CLKin1_OUT_MUX, CLKin0_OUT_MUX

Table 38. Register 0x147

BIT	NAME	POR DEFAULT	DESCRIPTION
7	CLKin_SEL_POL	0	Inverts the CLKin polarity for use in pin select mode. 0: Active High 1: Active Low
6:4	CLKin_SEL_MODE	3	Sets the mode used in determining the reference for PLL1.
			Field Value	CLKin Mode
			0 (0x00)	CLKin0 Manual
			1 (0x01)	CLKin1 Manual
			2 (0x02)	CLKin2 Manual
			3 (0x03)	Pin Select Mode
			4 (0x04)	Auto Mode
			5 (0x05)	Reserved
			6 (0x06)	Reserved
			7 (0x07)	Reserved
3:2	CLKin1_OUT_MUX	2	Selects where the output of the CLKin1 buffer is directed.
			Field Value	CLKin1 Destination
			0 (0x00)	Fin
			1 (0x01)	Feedback Mux (0-delay mode)
			2 (0x02)	PLL1
			3 (0x03)	Off
1:0	CLKin0_OUT_MUX	2	Selects where the output of the CLKin0 buffer is directed.
			Field Value	CLKin0 Destination
			0 (0x00)	SYSREF Mux
			1 (0x01)	Reserved
			2 (0x02)	PLL1
			3 (0x03)	Off

9.7.4.3 CLKin_SEL0_MUX, CLKin_SEL0_TYPE

This register has CLKin_SEL0 controls.

Table 39. Register 0x148

BIT	NAME	POR DEFAULT	DESCRIPTION
7:6	NA	0	Reserved
5:3	CLKin_SEL0_MUX	0	This set the output value of the CLKin_SEL0 pin. This register only applies if CLKin_SEL0_TYPE is set to an output mode
			Field Value	Output Format
			0 (0x00)	Logic Low
			1 (0x01)	CLKin0 LOS
			2 (0x02)	CLKin0 Selected
			3 (0x03)	DAC Locked
			4 (0x04)	DAC Low
			5 (0x05)	DAC High
			6 (0x06)	SPI Readback
			7 (0x07)	Reserved
2:0	CLKin_SEL0_TYPE	2	This sets the IO type of the CLKin_SEL0 pin.
			Field Value	Configuration	Function
			0 (0x00)	Input	Input mode, see Input Clock Switching - Pin Select Mode for description of input mode.
			1 (0x01)	Input /w pull-up resistor
			2 (0x02)	Input /w pull-down resistor
			3 (0x03)	Output (push-pull)	Output modes; the CLKin_SEL0_MUX register for description of outputs.
			4 (0x04)	Output inverted (push-pull)
			5 (0x05)	Reserved
			6 (0x06)	Output (open drain)

9.7.4.4 SDIO_RDBK_TYPE, CLKin_SEL1_MUX, CLKin_SEL1_TYPE

This register has CLKin_SEL1 controls and register readback SDIO pin type.

Table 40. Register 0x149

BIT	NAME	POR DEFAULT	DESCRIPTION
7	NA	0	Reserved
6	SDIO_RDBK_TYPE	1	Sets the SDIO pin to open drain when during SPI readback in 3 wire mode. 0: Output, push-pull 1: Output, open drain.
5:3	CLKin_SEL1_MUX	0	This set the output value of the CLKin_SEL1 pin. This register only applies if CLKin_SEL1_TYPE is set to an output mode.
			Field Value	Output Format
			0 (0x00)	Logic Low
			1 (0x01)	CLKin1 LOS
			2 (0x02)	CLKin1 Selected
			3 (0x03)	DAC Locked
			4 (0x04)	DAC Low
			5 (0x05)	DAC High
			6 (0x06)	SPI Readback
			7 (0x07)	Reserved
2:0	CLKin_SEL1_TYPE	2	This sets the IO type of the CLKin_SEL1 pin.
			Field Value	Configuration	Function
			0 (0x00)	Input	Input mode, see Input Clock Switching - Pin Select Mode for description of input mode.
			1 (0x01)	Input /w pull-up resistor
			2 (0x02)	Input /w pull-down resistor
			3 (0x03)	Output (push-pull)	Output modes; see the CLKin_SEL1_MUX register for description of outputs.
			4 (0x04)	Output inverted (push-pull)
			5 (0x05)	Reserved
			6 (0x06)	Output (open drain)

9.7.5 RESET_MUX, RESET_TYPE

This register contains control of the RESET pin.

Table 41. Register 0x14A

BIT	NAME	POR DEFAULT	DESCRIPTION
7:6	NA	0	Reserved
5:3	RESET_MUX	0	This sets the output value of the RESET pin. This register only applies if RESET_TYPE is set to an output mode.
			Field Value	Output Format
			0 (0x00)	Logic Low
			1 (0x01)	Reserved
			2 (0x02)	CLKin2 Selected
			3 (0x03)	DAC Locked
			4 (0x04)	DAC Low
			5 (0x05)	DAC High
			6 (0x06)	SPI Readback
2:0	RESET_TYPE	2	This sets the IO type of the RESET pin.
			Field Value	Configuration	Function
			0 (0x00)	Input	Reset Mode Reset pin high = Reset
			1 (0x01)	Input /w pull-up resistor
			2 (0x02)	Input /w pull-down resistor
			3 (0x03)	Output (push-pull)	Output modes; see the RESET_MUX register for description of outputs.
			4 (0x04)	Output inverted (push-pull)
			5 (0x05)	Reserved
			6 (0x06)	Output (open drain)

9.7.6 (0x14B - 0x152) Holdover

9.7.6.1 LOS_TIMEOUT, LOS_EN, TRACK_EN, HOLDOVER_FORCE, MAN_DAC_EN, MAN_DAC[9:8]

This register contains the holdover functions.

Table 42. Register 0x14B

BIT	NAME	POR DEFAULT	DESCRIPTION
7:6	LOS_TIMEOUT	0	This controls the amount of time in which no activity on a CLKin forces a clock switch event.
			Field Value	Timeout
			0 (0x00)	370 kHz
			1 (0x01)	2.1 MHz
			2 (0x02)	8.8 MHz
			3 (0x03)	22 MHz
5	LOS_EN	0	Enables the LOS (Loss-of-Signal) timeout control. Valid for MOS clock inputs. 0: Disabled 1: Enabled
4	TRACK_EN	1	Enable the DAC to track the PLL1 tuning voltage, optionally for use in holdover mode. After device reset, tracking starts at DAC code = 512. Tracking can be used to monitor PLL1 voltage in any mode. 0: Disabled 1: Enabled, will only track when PLL1 is locked.
3	HOLDOVER _FORCE	0	This bit forces holdover mode. When holdover mode is forced, if MAN_DAC_EN = 1, then the DAC will set the programmed MAN_DAC value. Otherwise the tracked DAC value will set the DAC voltage. 0: Disabled 1: Enabled.
2	MAN_DAC_EN	1	This bit enables the manual DAC mode. 0: Automatic 1: Manual
1:0	MAN_DAC[9:8]	2	See MAN_DAC[9:8], MAN_DAC[7:0] for more information on the MAN_DAC settings.

9.7.6.2 MAN_DAC[9:8], MAN_DAC[7:0]

These registers set the value of the DAC in holdover mode when used manually.

Table 43. MAN_DAC[9:0]

MSB	LSB
0x14B[1:0]	0x14C[7:0]

BIT	REGISTERS	NAME	POR DEFAULT	DESCRIPTION
7:2	0x14B			See LOS_TIMEOUT, LOS_EN, TRACK_EN, HOLDOVER_FORCE, MAN_DAC_EN, MAN_DAC[9:8] for information on these bits.
1:0	0x14B	MAN_DAC[9:8]	2	Sets the value of the manual DAC when in manual DAC mode.
				Field Value	DAC Value
				0 (0x00)	0
				1 (0x01)	1
7:0	0x14C	MAN_DAC[7:0]	0	2 (0x02)	2
				...	...
				1022 (0x3FE)	1022
				1023 (0x3FF)	1023

9.7.6.3 DAC_TRIP_LOW

This register contains the high value at which holdover mode is entered.

Table 44. Register 0x14D

BIT	NAME	POR DEFAULT	DESCRIPTION
7:6	NA	0	Reserved
5:0	DAC_TRIP_LOW	0	Voltage from GND at which holdover is entered if HOLDOVER_VTUNE_DET is enabled.
			Field Value	DAC Trip Value
			0 (0x00)	1 x Vcc / 64
			1 (0x01)	2 x Vcc / 64
			2 (0x02)	3 x Vcc / 64
			3 (0x03)	4 x Vcc / 64
			...	...
			61 (0x17)	62 x Vcc / 64
			62 (0x18)	63 x Vcc / 64
			63 (0x19)	64 x Vcc / 64

9.7.6.4 DAC_CLK_MULT, DAC_TRIP_HIGH

This register contains the multiplier for the DAC clock counter and the low value at which holdover mode is entered.

Table 45. Register 0x14E

BIT	NAME	POR DEFAULT	DESCRIPTION
7:6	DAC_CLK_MULT	0	This is the multiplier for the DAC_CLK_CNTR which sets the rate at which the DAC value is tracked.
			Field Value	DAC Multiplier Value
			0 (0x00)	4
			1 (0x01)	64
			2 (0x02)	1024
			3 (0x03)	16384
5:0	DAC_TRIP_HIGH	0	Voltage from Vcc at which holdover is entered if HOLDOVER_VTUNE_DET is enabled.
			Field Value	DAC Trip Value
			0 (0x00)	1 x Vcc / 64
			1 (0x01)	2 x Vcc / 64
			2 (0x02)	3 x Vcc / 64
			3 (0x03)	4 x Vcc / 64
			...	...
			61 (0x17)	62 x Vcc / 64
			62 (0x18)	63 x Vcc / 64
			63 (0x19)	64 x Vcc / 64

9.7.6.5 DAC_CLK_CNTR

This register contains the value of the DAC when in tracked mode.

Table 46. Register 0x14F

BIT	NAME	POR DEFAULT	DESCRIPTION
7:0	DAC_CLK_CNTR	127	This with DAC_CLK_MULT set the rate at which the DAC is updated. The update rate is = DAC_CLK_MULT * DAC_CLK_CNTR / PLL1 PDF
			Field Value	DAC Value
			0 (0x00)	0
			1 (0x01)	1
			2 (0x02)	2
			3 (0x03)	3
			...	...
			253 (0xFD)	253
			254 (0xFE)	254
			255 (0xFF)	255

9.7.6.6 CLKin_OVERRIDE, HOLDOVER_PLL1_DET, HOLDOVER_LOS_DET, HOLDOVER_VTUNE_DET, HOLDOVER_HITLESS_SWITCH, HOLDOVER_EN

This register has controls for enabling clock in switch events.

Table 47. Register 0x150

BIT	NAME	POR DEFAULT	DESCRIPTION
7	NA	0	Reserved
6	CLKin _OVERRIDE	0	When CLKin_SEL_MODE = 0/1/2 to select a manual clock input, CLKin_OVERRIDE = 1 will force that clock input. Used with clock distribution mode for best performance. 0: Normal, no override. 1: Force select of only CLKin0/1/2 as specified by CLKin_SEL_MODE in manual mode.
5	NA	0	Reserved
4	HOLDOVER _PLL1_DET	0	This enables the HOLDOVER when PLL1 lock detect signal transitions from high to low. 0: PLL1 DLD does not cause a clock switch event 1: PLL1 DLD causes a clock switch event
3	HOLDOVER _LOS_DET	0	This enables HOLDOVER when PLL1 LOS signal is detected. 0: Disabled 1: Enabled
2	HOLDOVER _VTUNE_DET	0	Enables the DAC Vtune rail detections. When the DAC achieves a specified Vtune, if this bit is enabled, the current clock input is considered invalid and an input clock switch event is generated. 0: Disabled 1: Enabled
1	HOLDOVER _HITLESS _SWITCH	1	Determines whether a clock switch event will enter holdover use hitless switching. 0: Hard Switch 1: Hitless switching (has an undefined switch time)
0	HOLDOVER_EN	1	Sets whether holdover mode is active or not. 0: Disabled 1: Enabled

9.7.6.7 HOLDOVER_DLD_CNT[13:8], HOLDOVER_DLD_CNT[7:0]

Table 48. HOLDOVER_DLD_CNT[13:0]

MSB	LSB
0x151[5:0]	0x152[7:0]

This register has the number of valid clocks of PLL1 PDF before holdover is exited.

Table 49. Registers 0x151 and 0x152

BIT	REGISTERS	NAME	POR DEFAULT	DESCRIPTION
7:6	0x151	NA	0	Reserved
5:0	0x151	HOLDOVER _DLD_CNT[13:8]	2	The number of valid clocks of PLL1 PDF before holdover mode is exited.
				Field Value	Count Value
				0 (0x00)	0
				1 (0x01)	1
7:0	0x152	HOLDOVER _DLD_CNT[7:0]	0	2 (0x02)	2
				...	...
				16382 (0x3FFE)	16382
				16383 (0x3FFF)	16383

9.7.7 (0x153 - 0x15F) PLL1 Configuration

9.7.7.1 CLKin0_R[13:8], CLKin0_R[7:0]

Table 50. CLKin0_R[13:0]

MSB	LSB
0x153[5:0]	0x154[7:0]

These registers contain the value of the CLKin0 divider.

BIT	REGISTERS	NAME	POR DEFAULT	DESCRIPTION
7:6	0x153	NA	0	Reserved
5:0	0x153	CLKin0_R[13:8]	0	The value of PLL1 N counter when CLKin0 is selected.
				Field Value	Divide Value
				0 (0x00)	Reserved
				1 (0x01)	1
7:0	0x154	CLKin0_R[7:0]	120	2 (0x02)	2
				...	...
				16382 (0x3FFE)	16382
				16383 (0x3FFF)	16383

9.7.7.2 CLKin1_R[13:8], CLKin1_R[7:0]

Table 51. CLKin1_R[13:0]

MSB	LSB
0x155[5:0]	0x156[7:0]

These registers contain the value of the CLKin1 R divider.

Table 52. Registers 0x155 and 0x156

BIT	REGISTERS	NAME	POR DEFAULT	DESCRIPTION
7:6	0x155	NA	0	Reserved
5:0	0x155	CLKin1_R[13:8]	0	The value of PLL1 N counter when CLKin1 is selected.
				Field Value	Divide Value
				0 (0x00)	Reserved
				1 (0x01)	1
7:0	0x156	CLKin1_R[7:0]	150	2 (0x02)	2
				...	...
				16382 (0x3FFE)	16382
				16383 (0x3FFF)	16383

9.7.7.3 CLKin2_R[13:8], CLKin2_R[7:0]

MSB	LSB
0x157[5:0]	0x158[7:0]

Table 53. Registers 0x157 and 0x158

BIT	REGISTERS	NAME	POR DEFAULT	DESCRIPTION
7:6	0x157	NA	0	Reserved
5:0	0x157	CLKin2_R[13:8]	0	The value of PLL1 N counter when CLKin2 is selected.
				Field Value	Divide Value
				0 (0x00)	Reserved
				1 (0x01)	1
7:0	0x158	CLKin2_R[7:0]	150	2 (0x02)	2
				...	...
				16382 (0x3FFE)	16382
				16383 (0x3FFF)	16383

9.7.7.4 PLL1_N

Table 54. PLL1_N[13:8], PLL1_N[7:0]

PLL1_N[13:0]
MSB	LSB
0x159[5:0]	0x15A[7:0]

These registers contain the N divider value for PLL1.

Table 55. Registers 0x159 and 0x15A

BIT	REGISTERS	NAME	POR DEFAULT	DESCRIPTION
7:6	0x159	NA	0	Reserved
5:0	0x159	PLL1_N[13:8]	0	The value of PLL1 N counter.
				Field Value	Divide Value
				0 (0x00)	Not Valid
				1 (0x01)	1
7:0	0x15A	PLL1_N[7:0]	120	2 (0x02)	2
				...	...
				4,095 (0xFFF)	4,095

9.7.7.5 PLL1_WND_SIZE, PLL1_CP_TRI, PLL1_CP_POL, PLL1_CP_GAIN

This register controls the PLL1 phase detector.

Table 56. Register 0x15B

BIT	NAME	POR DEFAULT	DESCRIPTION
7:6	PLL1_WND_SIZE	3	PLL1_WND_SIZE sets the window size used for digital lock detect for PLL1. If the phase error between the reference and feedback of PLL1 is less than specified time, then the PLL1 lock counter increments.
			Field Value	Definition
			0 (0x00)	4 ns
			1 (0x01)	9 ns
			2 (0x02)	19 ns
			3 (0x03)	43 ns
5	PLL1_CP_TRI	0	This bit allows for the PLL1 charge pump output pin, CPout1, to be placed into TRI-STATE. 0: PLL1 CPout1 is active 1: PLL1 CPout1 is at TRI-STATE
4	PLL1_CP_POL	1	PLL1_CP_POL sets the charge pump polarity for PLL1. Many VCXOs use positive slope. A positive slope VCXO increases output frequency with increasing voltage. A negative slope VCXO decreases output frequency with increasing voltage. 0: Negative Slope VCO/VCXO 1: Positive Slope VCO/VCXO
3:0	PLL1_CP_GAIN	4	This bit programs the PLL1 charge pump output current level.
			Field Value	Gain
			0 (0x00)	50 µA
			1 (0x01)	150 µA
			2 (0x02)	250 µA
			3 (0x03)	350 µA
			4 (0x04)	450 µA
			...	...
			14 (0x0E)	1450 µA
			15 (0x0F)	1550 µA

9.7.7.6 PLL1_DLD_CNT[13:8], PLL1_DLD_CNT[7:0]

Table 57. PLL1_DLD_CNT[13:0]

MSB	LSB
0x15C[5:0]	0x15D[7:0]

This register contains the value of the PLL1 DLD counter.

Table 58. Registers 0x15C and 0x15D

BIT	REGISTERS	NAME	POR DEFAULT	DESCRIPTION
7:6	0x15C	NA	0	Reserved
5:0	0x15C	PLL1_DLD _CNT[13:8]	32	The reference and feedback of PLL1 must be within the window of phase error as specified by PLL1_WND_SIZE for this many phase detector cycles before PLL1 digital lock detect is asserted.
				Field Value	Delay Value
				0 (0x00)	Reserved
				1 (0x01)	1
7:0	0x15D	PLL1_DLD _CNT[7:0]	0	2 (0x02)	2
				3 (0x03)	3
				...	...
				16,382 (0x3FFE)	16,382
				16,383 (0x3FFF)	16,383

9.7.7.7 PLL1_R_DLY, PLL1_N_DLY

This register contains the delay value for PLL1 N and R delays.

Table 59. Register 0x15E

BIT	NAME	POR DEFAULT	DESCRIPTION
7:6	NA	0	Reserved
5:3	PLL1_R_DLY	0	Increasing delay of PLL1_R_DLY will cause the outputs to lag from CLKinX. For use in 0-delay mode.
			Field Value	Gain
			0 (0x00)	0 ps
			1 (0x01)	205 ps
			2 (0x02)	410 ps
			3 (0x03)	615 ps
			4 (0x04)	820 ps
			5 (0x05)	1025 ps
			6 (0x06)	1230 ps
			7 (0x07)	1435 ps
2:0	PLL1_N_DLY	0	Increasing delay of PLL1_N_DLY will cause the outputs to lead from CLKinX. For use in 0-delay mode.
			Field Value	Gain
			0 (0x00)	0 ps
			1 (0x01)	205 ps
			2 (0x02)	410 ps
			3 (0x03)	615 ps
			4 (0x04)	820 ps
			5 (0x05)	1025 ps
			6 (0x06)	1230 ps
			7 (0x07)	1435 ps

9.7.7.8 PLL1_LD_MUX, PLL1_LD_TYPE

This register configures the PLL1 LD pin.

Table 60. Register 0x15F

BIT	NAME	POR DEFAULT	DESCRIPTION
7:3	PLL1_LD_MUX	1	This sets the output value of the Status_LD1 pin.
			Field Value	MUX Value
			0 (0x00)	Logic Low
			1 (0x01)	PLL1 DLD
			2 (0x02)	PLL2 DLD
			3 (0x03)	PLL1 & PLL2 DLD
			4 (0x04)	Holdover Status
			5 (0x05)	DAC Locked
			6 (0x06)	Reserved
			7 (0x07)	SPI Readback
			8 (0x08)	DAC Rail
			9 (0x09)	DAC Low
			10 (0x0A)	DAC High
			11 (0x0B)	PLL1_N
			12 (0x0C)	PLL1_N/2
			13 (0x0D)	PLL2_N
			14 (0x0E)	PLL2_N/2
			15 (0x0F)	PLL1_R
			16 (0x10)	PLL1_R/2
			17 (0x11)	PLL2_R⁽¹⁾
			18 (0x12)	PLL2_R/2⁽¹⁾
2:0	PLL1_LD_TYPE	6	Sets the IO type of the Status_LD1 pin.
			Field Value	TYPE
			0 (0x00)	Reserved
			1 (0x01)	Reserved
			2 (0x02)	Reserved
			3 (0x03)	Output (push-pull)
			4 (0x04)	Output inverted (push-pull)
			5 (0x05)	Reserved
			6 (0x06)	Output (open drain)

(1) Only valid when PLL2_LD_MUX is not set to 2 (PLL2_DLD) or 3 (PLL1 & PLL2 DLD).

9.7.8 (0x160 - 0x16E) PLL2 Configuration

9.7.8.1 PLL2_R[11:8], PLL2_R[7:0]

Table 61. PLL2_R[11:0]

MSB	LSB
0x160[3:0]	0x161[7:0]

This register contains the value of the PLL2 R divider.

Table 62. Registers 0x160 and 0x161

BIT	REGISTERS	NAME	POR DEFAULT	DESCRIPTION
7:4	0x160	NA	0	Reserved
3:0	0x160	PLL2_R[11:8]	0	Valid values for the PLL2 R divider.
				Field Value	Divide Value
				0 (0x00)	Not Valid
				1 (0x01)	1
7:0	0x161	PLL2_R[7:0]	2	2 (0x02)	2
				3 (0x03)	3
				...	...
				4,094 (0xFFE)	4,094
				4,095 (0xFFF)	4,095

9.7.8.2 PLL2_P, OSCin_FREQ, PLL2_XTAL_EN, PLL2_REF_2X_EN

This register sets other PLL2 functions.

Table 63. Register 0x162

BIT	NAME	POR DEFAULT	DESCRIPTION
7:5	PLL2_P	2	The PLL2 N Prescaler divides the output of the VCO as selected by Mode_MUX1 and is connected to the PLL2 N divider.
			Field Value	Value
			0 (0x00)	8
			1 (0x01)	2
			2 (0x02)	2
			3 (0x03)	3
			4 (0x04)	4
			5 (0x05)	5
			6 (0x06)	6
			7 (0x07)	7
4:2	OSCin_FREQ	7	The frequency of the PLL2 reference input to the PLL2 Phase Detector (OSCin/OSCin* port) must be programmed in order to support proper operation of the frequency calibration routine which locks the internal VCO to the target frequency.
			Field Value	OSCin Frequency
			0 (0x00)	0 to 63 MHz
			1 (0x01)	>63 MHz to 127 MHz
			2 (0x02)	>127 MHz to 255 MHz
			3 (0x03)	Reserved
			4 (0x04)	>255 MHz to 500 MHz
			5 (0x05) to 7(0x07)	Reserved
1	PLL2_XTAL_EN	0	If an external crystal is being used to implement a discrete VCXO, the internal feedback amplifier must be enabled with this bit in order to complete the oscillator circuit. 0: Oscillator Amplifier Disabled 1: Oscillator Amplifier Enabled
0	PLL2_REF_2X_EN	1	Enabling the PLL2 reference frequency doubler allows for higher phase detector frequencies on PLL2 than would normally be allowed with the given VCXO or Crystal frequency. Higher phase detector frequencies reduces the PLL N values which makes the design of wider loop bandwidth filters possible. 0: Doubler Disabled 1: Doubler Enabled

9.7.8.3 PLL2_N_CAL

PLL2_N_CAL[17:0]

PLL2 never uses 0-delay during frequency calibration. These registers contain the value of the PLL2 N divider used with PLL2 pre-scaler during calibration for cascaded 0-delay mode. Once calibration is complete, PLL2 will use PLL2_N value. Cascaded 0-delay mode occurs when PLL2_NCLK_MUX = 1.

Table 64. Register 0x162

MSB	—	LSB
0x163[1:0]	0x164[7:0]	0x165[7:0]

Table 65. Registers 0x163, 0x164, and 0x165

BIT	REGISTERS	NAME	POR DEFAULT	DESCRIPTION
7:2	0x163	NA	0	Reserved
1:0	0x163	PLL2_N _CAL[17:16]	0	Field Value	Divide Value
1:0	0x163	PLL2_N _CAL[17:16]	0	0 (0x00)	Not Valid
7:0	0x164	PLL2_N_CAL[15:8]	0	1 (0x01)	1
7:0	0x164	PLL2_N_CAL[15:8]	0	2 (0x02)	2
7:0	0x165	PLL2_N_CAL[7:0]	12	...	...
7:0	0x165	PLL2_N_CAL[7:0]	12	262,143 (0x3FFFF)	262,143

9.7.8.4 PLL2_FCAL_DIS, PLL2_N

This register disables frequency calibration and sets the PLL2 N divider value. Programming register 0x168 starts a VCO calibration routine if PLL2_FCAL_DIS = 0.

Table 66. PLL2_N[17:0]

MSB	—	LSB
0x166[1:0]	0x167[7:0]	0x168[7:0]

Table 67. Registers 0x166, 0x167, and 0x168

BIT	REGISTERS	NAME	POR DEFAULT	DESCRIPTION
7:3	0x166	NA	0	Reserved
2	0x166	PLL2_FCAL_DIS	0	This disables the PLL2 frequency calibration on programming register 0x168. 0: Frequency calibration enabled 1: Frequency calibration disabled
1:0	0x166	PLL2_N[17:16]	0	Field Value	Divide Value
1:0	0x166	PLL2_N[17:16]	0	0 (0x00)	Not Valid
7:0	0x167	PLL2_N[15:8]	0	1 (0x01)	1
7:0	0x167	PLL2_N[15:8]	0	2 (0x02)	2
7:0	0x168	PLL2_N[7:0]	12	...	...
7:0	0x168	PLL2_N[7:0]	12	262,143 (0x3FFFF)	262,143

9.7.8.5 PLL2_WND_SIZE, PLL2_CP_GAIN, PLL2_CP_POL, PLL2_CP_TRI

This register controls the PLL2 phase detector.

Table 68. Register 0x169

BIT	NAME	POR DEFAULT	DESCRIPTION
7	NA	0	Reserved
6:5	PLL2_WND_SIZE	2	PLL2_WND_SIZE sets the window size used for digital lock detect for PLL2. If the phase error between the reference and feedback of PLL2 is less than specified time, then the PLL2 lock counter increments. This value must be programmed to 2 (3.7 ns).
			Field Value	Definition
			0 (0x00)	Reserved
			1 (0x01)	Reserved
			2 (0x02)	3.7 ns
			3 (0x03)	Reserved
4:3	PLL2_CP_GAIN	3	This bit programs the PLL2 charge pump output current level. The table below also illustrates the impact of the PLL2 TRISTATE bit in conjunction with PLL2_CP_GAIN.
			Field Value	Definition
			0 (0x00)	100 µA
			1 (0x01)	400 µA
			2 (0x02)	1600 µA
			3 (0x03)	3200 µA
2	PLL2_CP_POL	0	PLL2_CP_POL sets the charge pump polarity for PLL2. The internal VCO requires the negative charge pump polarity to be selected. Many VCOs use positive slope. A positive slope VCO increases output frequency with increasing voltage. A negative slope VCO decreases output frequency with increasing voltage.
			Field Value	Description
			0	Negative Slope VCO/VCXO
			1	Positive Slope VCO/VCXO
1	PLL2_CP_TRI	0	PLL2_CP_TRI TRI-STATEs the output of the PLL2 charge pump. 0: Disabled 1: TRI-STATE
0	Fixed Value	1	When programming register 0x169, this field must be set to 1.

9.7.8.6 SYSREF_REQ_EN, PLL2_DLD_CNT

Table 69. PLL2_DLD_CNT[15:0]

MSB	LSB
0x16A[5:0]	0x16B[7:0]

This register has the value of the PLL2 DLD counter.

Table 70. Registers 0x16A and 0x16B

BIT	REGISTERS	NAME	POR DEFAULT	DESCRIPTION
7	0x16A	NA	0	Reserved
6	0x16A	SYSREF_REQ_EN	0	Enables the SYNC/SYSREF_REQ pin to force the SYSREF_MUX = 3 for continuous pulses. When using this feature enable pulser and set SYSREF_MUX = 2 (Pulser).
5:0	0x16A	PLL2_DLD _CNT[13:8]	32	The reference and feedback of PLL2 must be within the window of phase error as specified by PLL2_WND_SIZE for PLL2_DLD_CNT cycles before PLL2 digital lock detect is asserted.
				Field Value	Divide Value
				0 (0x00)	Not Valid
				1 (0x01)	1
7:0	0x16B	PLL2_DLD_CNT	0	2 (0x02)	2
				3 (0x03)	3
				...	...
				16,382 (0x3FFE)	16,382
				16,383 (0x3FFF)	16,383

9.7.8.7 PLL2_LF_R4, PLL2_LF_R3

This register controls the integrated loop filter resistors.

Table 71. Register 0x16C

BIT	NAME	POR DEFAULT	DESCRIPTION
7:6	NA	0	Reserved
5:3	PLL2_LF_R4	0	Internal loop filter components are available for PLL2, enabling either 3rd or 4th order loop filters without requiring external components. Internal loop filter resistor R4 can be set according to the following table.
			Field Value	Resistance
			0 (0x00)	200 Ω
			1 (0x01)	1 kΩ
			2 (0x02)	2 kΩ
			3 (0x03)	4 kΩ
			4 (0x04)	16 kΩ
			5 (0x05)	Reserved
			6 (0x06)	Reserved
			7 (0x07)	Reserved
2:0	PLL2_LF_R3	0	Internal loop filter components are available for PLL2, enabling either 3rd or 4th order loop filters without requiring external components. Internal loop filter resistor R3 can be set according to the following table.
			Field Value	Resistance
			0 (0x00)	200 Ω
			1 (0x01)	1 kΩ
			2 (0x02)	2 kΩ
			3 (0x03)	4 kΩ
			4 (0x04)	16 kΩ
			5 (0x05)	Reserved
			6 (0x06)	Reserved
			7 (0x07)	Reserved

9.7.8.8 PLL2_LF_C4, PLL2_LF_C3

This register controls the integrated loop filter capacitors.

Table 72. Register 0x16D

BIT	NAME	POR DEFAULT	DESCRIPTION
7:4	PLL2_LF_C4	0	Internal loop filter components are available for PLL2, enabling either 3rd or 4th order loop filters without requiring external components. Internal loop filter capacitor C4 can be set according to the following table.
			Field Value	Capacitance
			0 (0x00)	10 pF
			1 (0x01)	15 pF
			2 (0x02)	29 pF
			3 (0x03)	34 pF
			4 (0x04)	47 pF
			5 (0x05)	52 pF
			6 (0x06)	66 pF
			7 (0x07)	71 pF
			8 (0x08)	103 pF
			9 (0x09)	108 pF
			10 (0x0A)	122 pF
			11 (0x0B)	126 pF
			12 (0x0C)	141 pF
			13 (0x0D)	146 pF
			14 (0x0E)	Reserved
			15 (0x0F)	Reserved
3:0	PLL2_LF_C3	0	Internal loop filter components are available for PLL2, enabling either 3rd or 4th order loop filters without requiring external components. Internal loop filter capacitor C3 can be set according to the following table.
			Field Value	Capacitance
			0 (0x00)	10 pF
			1 (0x01)	11 pF
			2 (0x02)	15 pF
			3 (0x03)	16 pF
			4 (0x04)	19 pF
			5 (0x05)	20 pF
			6 (0x06)	24 pF
			7 (0x07)	25 pF
			8 (0x08)	29 pF
			9 (0x09)	30 pF
			10 (0x0A)	33 pF
			11 (0x0B)	34 pF
			12 (0x0C)	38 pF
			13 (0x0D)	39 pF
			14 (0x0E)	Reserved
			15 (0x0F)	Reserved

9.7.8.9 PLL2_LD_MUX, PLL2_LD_TYPE

This register sets the output value of the Status_LD2 pin.

Table 73. Register 0x16E

BIT	NAME	POR DEFAULT	DESCRIPTION
7:3	PLL2_LD_MUX	2	This sets the output value of the Status_LD2 pin.
			Field Value	MUX Value
			0 (0x00)	Logic Low
			1 (0x01)	PLL1 DLD
			2 (0x02)	PLL2 DLD
			3 (0x03)	PLL1 & PLL2 DLD
			4 (0x04)	Holdover Status
			5 (0x05)	DAC Locked
			6 (0x06)	Reserved
			7 (0x07)	SPI Readback
			8 (0x08)	DAC Rail
			9 (0x09)	DAC Low
			10 (0x0A)	DAC High
			11 (0x0B)	PLL1_N
			12 (0x0C)	PLL1_N/2
			13 (0x0D)	PLL2_N
			14 (0x0E)	PLL2_N/2
			15 (0x0F)	PLL1_R
			16 (0x10)	PLL1_R/2
			17 (0x11)	PLL2_R⁽¹⁾
			18 (0x12)	PLL2_R/2⁽¹⁾
2:0	PLL2_LD_TYPE	6	Sets the IO type of the Status_LD2 pin.
			Field Value	TYPE
			0 (0x00)	Reserved
			1 (0x01)	Reserved
			2 (0x02)	Reserved
			3 (0x03)	Output (push-pull)
			4 (0x04)	Output inverted (push-pull)
			5 (0x05)	Reserved
			6 (0x06)	Output (open drain)

(1) Only valid when PLL1_LD_MUX is not set to 2 (PLL2_DLD) or 3 (PLL1 & PLL2 DLD).

9.7.9 (0x16F - 0x1FFF) Misc Registers

9.7.9.1 Fixed Register 0x171

Always program this register to value 170.

Table 74. Register 0x171

BIT	NAME	POR DEFAULT	DESCRIPTION
7:0	Fixed Register	10 (0x0A)	Always program to 170 (0xAA)

9.7.9.2 Fixed Register 0x172

Always program this register to value 2.

Table 75. Register 0x172

BIT	NAME	POR DEFAULT	DESCRIPTION
7:0	Fixed Register	0	Always program to 2 (0x02)

9.7.9.3 PLL2_PRE_PD, PLL2_PD

Table 76. Register 0x173

BIT	NAME	DESCRIPTION
7	N/A	Reserved
6	PLL2_PRE_PD	Powerdown PLL2 prescaler 0: Normal Operation 1: Powerdown
5	PLL2_PD	Powerdown PLL2 0: Normal Operation 1: Powerdown
4:0	N/A	Reserved

9.7.9.4 OPT_REG_1

This register must be written to optimize VCO1 phase noise performance over temperature. This register must be written before writing register 0x168 for PLL2 calibration when using VCO1.

Table 77. Register 0x17C

BIT	NAME	DESCRIPTION
7:0	OPT_REG_1	Program to 21 (0x15)

9.7.9.5 OPT_REG_2