9.1 Overview

The LMK0482x family are multi-purpose, jitter cleaning dual-PLL circuits, with user-programmable settings to support a flexible set of configurations for many different application requirements. PLL1 is optimized for use with an external VCXO as the PLL oscillator, while PLL2 includes a dual-range integrated VCO and distributes the VCO output to 7 integrated 10-bit channel dividers and a 13-bit SYSREF divider, yielding a total of 14 differential clock outputs at up to 8 different frequencies.

The primary use case is as a dual-loop jitter cleaner (dual-loop mode), when using a reference clock with good frequency accuracy but poor phase noise to generate ultra-low jitter output clocks. Dual-loop mode also helps to maintain a high phase detector frequency and loop bandwidth in the clock generation PLL when the greatest common divisor of the reference clock frequency and the output clock frequencies is small, avoiding a low phase detector frequency that would elevate output clock phase noise.

Both PLLs can optionally be disabled. By disabling PLL1, the LMK0482x can be used as a standard single-PLL clock generator with integrated VCO (single-loop mode). By disabling both PLLs, the LMK0482x can act as a distribution buffer/divider, directly connecting an input reference to the clock dividers and the SYSREF divider. The clock output dividers can also be bypassed or set to divide of 1 for distribution only mode.

In a typical dual-loop configuration, the external VCXO is connected to the PLL1 N-divider, and the integrated VCO is connected to the N-divider directly. However, by routing the divided clock or SYSREF output of PLL2 to the N-divider of PLL1, PLL2, or both PLLs in a family of configurations called zero-delay mode, the LMK0482x can establish a deterministic phase relationship between reference input phase and clock output phase. Using zero-delay mode, multiple LMK0482x can be cascaded to fan out exponentially more outputs, while maintaining predictable input-to-output phase throughout the whole chain of devices. Zero-delay mode is supported in singleloop and dual-loop mode, with two dual-loop configurations: nested dual-loop (feedback connected to PLL1 Ndivider) and cascaded dual-loop (feedback connected to PLL2 N-divider).

The LMK0482x may be used in JESD204B sytems by providing a device clock and SYSREF to up to 7 devices. However, alternate (non-JESD204B) systems are also possible by programming pairs of outputs to share the clock divider. Any mix of JESD204B and alternate systems can be supported.