10.6.1 System Level Diagram

Figure 40 and Figure 41 show an LMK0482x family device with external circuitry for clocking and for power supply to serve as a guideline for good practices when designing with the LMK0482x family. Refer to Pin Connection Recommendations for more details on the pin connections and bypassing recommendations. Also refer to the evaluation board in LMK04826/28 User's Guide. PCB design will also play a role in device performance.

Figure 40 shows the primary reference clock input is at CLKin0/0*. A secondary reference clock is driving CLKin1/1*. Both clocks are depicted as AC-coupled drivers. The VCXO attached to the OSCin/OSCin* port is configured as an AC-coupled single-ended driver. Any of the input ports (CLKin0/0*, CLKin1/1*, CLKin2/2*, OSCin/OSCin*) may be configured as either differential or single-ended (see Driving CLKin and OSCin Inputs).

The loop filter for PLL1 is configured as a 2nd-order passive filter, while the loop filter for PLL2 is configured as a 4th order passive filter (using internal 3rd and 4th order components). Typically it is not necessary to increase the filter beyond 2nd order for PLL1. PLL2 allows software programmability of the 3rd and 4th order components (see PLL2 Integrated Loop Filter Poles). PLLatinum Sim can be used to compute the loop filter values for optimal phase noise.

All the LVPECL clock outputs are AC-coupled with 0.1 µF capacitors. Some LVPECL outputs are depicted with 240-Ω emitter resistors, and some are depicted with 150-Ω emitter resistors. LVPECL clock outputs can use emitter resistors between 120 Ω and 240 Ω. OSCout LVPECL format only supports 240-Ω emitter resistors is depicted with 240-Ω emitter resistors. The LCPECL SYSREF output is DC-coupled, with termination values matching the conditions specified for LCPECL in the Electrical Characteristics. The non-JESD204B LVDS outputs are AC-coupled, and include 560 Ω between the pins of the differential pair to create a DC path for current on startup (see LVDS/HSDS). The JESD204B LVDS outputs are DC-coupled. Unused outputs are left floating.

PCB design will influence crosstalk performance. Tightly coupled clock traces will have less crosstalk than loosely coupled clock traces. Proximity to other clock traces will influence crosstalk.

Figure 41 shows an example decoupling and bypassing scheme for the LMK0482x, which could apply to the configuration shown in Figure 40. Components drawn in dotted lines are optional (see Pin Connection Recommendations). Two power planes are used in these example designs, one for the clock outputs and one for the PLL circuits. It is possible to reduce the number of decoupling components by tying together clock output Vcc pins for CLKouts that share the same frequency or otherwise can tolerate potential crosstalk between outputs with different frequencies. In the two examples, Vcc2 and Vcc11 can be tied together since no outputs are utilized from Clock Group 0. PCB design will influence impedance to the supply. Vias and traces will increase the impedance to the power supply. Ensure good direct return current paths.