PLL2 OSCin input path includes an on-chip Frequency Doubler. To have the best phase noise performance, TI recommends to maximize the PLL2 phase detector frequency. For example, using 122.88-MHz VCXO, PLL2 phase detector frequency can be increased to 245.76 MHz by setting PLL2_REF_2X_EN. Doubler path is a high performance path for OSCin clock. For configuration where doubler cannot be used, TI recommends to use Doubler and PLL2_RDIV = 2. To have deterministic phase relationship between input clock and output clocks, 0-delay modes should be used (nested 0-delay mode for dual loop configuration instead of cascaded 0-delay mode).