ZHCSPJ6A October 2022 – November 2022 LMK04832-SEP
PRODUCTION DATA
The SYNC pin must be used to synchronized the PLL2 R divider. When PLL2R_SYNC_EN = 1, as long as the SYNC pin is held high, the PLL2 R divider is held in reset. When the SYNC pin is returned low, the divider is allowed to continue dividing. While PLL2R_SYNC_EN = 1 and SYNC pin is high PLL2 is unlocked.
It is necessary to meet a setup and hold time when SYNC pin goes low to ensure deterministic reset of the PLL2 R divider.
The SYNC_POL bit has no effect on SYNC polarity for PLL2 R synchronization.