Dynamic digital delay allows the phase of clocks to be changed with respect to each other with little impact to the clock signal.

For the device clock dividers this is accomplished by substituting the regular clock divider with an alternate divide value of one larger than the regular divider for one cycle. This substitution will occur a number of times equal to the value programmed into the DDLYd_STEP_CNT field for all outputs with DDLYdX_EN = 1.

For the SYSREF divider, an alternate divide value is substituted for the regular divide value. This substitution will occur a number of times equal to the value programmed into the DDLYd_STEP_CNT if DDLYd_SYSREF_EN = 1. To achieve one cycle delay as is done for the device clock dividers, set the SYSREF_DDLY value to one greater than SYSREF_DIV+SYSREF_DIV/2. For example, for a SYSREF divider of 100, to achieve 1 cycle delay, SYSREF_DDLY = 100 + 50 + 1 = 151.

While using the Dynamic Digital Delay feature, CLKin_OVERRIDE must be set to 0.

• By programming a larger alternate divider (delay) value, the phase of the adjusted outputs are delayed with respect to the other clocks.
• By programming a smaller alternate divider (delay) value, the phase of the adjusted outputs are advanced with respect to the other clocks.