The SYSREF divider includes a digital delay block which allows a global phase shift with respect to the device clocks.

Each clock output pair includes a local SYSREF analog and digital delay for unique phase adjustment of each SYSREF clock.

The local analog delay allows for approximately 21-ps steps. Turning-on analog delay adds an additional 124 ps of delay in the clock path. The digital delay step can be as small as half the period of the clock distribution path. For example, a 3.2-GHz VCO frequency results in 156.25-ps steps.

The local digital delay and half step allows a SYSREF output to be delayed from 1.5 to 11 clock distribution path cycles.