米6体育平台手机版

ZHCSPJ6A October 2022 – November 2022 LMK04832-SEP

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

PAP|64
- MPQF071C

散热焊盘机械数据 (封装 | 引脚)

PAP|64
- PPTD060M

订购信息

6.5 Electrical Characteristics

VDD, VDD_A = 3.3 V ± 5 %, –55 °C ≤T_A ≤ 125 °C. Typical values are at VDD = VDD_A = 3.3 V, 25 °C (unless otherwise noted)

SYMBOL	PARAMETER	TEST CONDITIONS		MIN	TYP	MAX	UNIT
Current Consumption
I_CC	Power Down Supply Current	Device Powered Down			3.3	5	mA
	Supply Current⁽¹⁾	PLL1 locked to external VCXO and PLL2 locked to internal VCO	4 CML 32 mA clocks in bypass 3 LVDS clock /12 4 SYSREF as LCPECL 3 SYSREF as LVDS		980
			4 CML 32 mA clocks in bypass 3 LVDS clock /12 4 SYSREF as LCPECL (low state) 3 SYSREF as LVDS (low state)		850
			4 CML 32 mA clocks in bypass 3 LVDS clock /12 7 SYSREF outputs powered down		700
CLKIN Specifications
f_CLKINx	LOS Circuitry	LOS_EN = 1		0.001		125	MHz
	PLL1	CLKinX-TYPE=1(MOS)	AC Coupled Input	0.001		250
	PLL1	CLKinX-TYPE=0 (Bipolar)	AC Coupled Input	0.001		750
	PLL2	CLKinX_TYPE=0 (Bipolar)	AC Coupled Input	0.001		500
	0-delay	0-delay with external feedback (CLKIN1)	AC Coupled Input	0.001		750
	Distribution Mode	CLKIN1/FIN1 Pin only	AC Coupled Input	0.001		3250
SLEW_CLKIN	Input Slew Rate⁽²⁾			0.15	0.5		V/ns
V_CLKINx/FIN1	Single-ended clock input voltage	Input pin AC coupled; complementary pin AC coupled to GND		0.5		2.4	Vpp
V_IDCLKINX/FIN1	Differential clock input voltage⁽³⁾	AC coupled		0.125		1.55	\|V\|
V_SSCLKINx/FIN1	Differential clock input voltage⁽³⁾	AC coupled		0.25		3.1	Vpp
\|V_CLKINX-offset\|	DC offset voltage between CLKIN /CLKINX* Each Pin AC Coupled	CLKIN0/1/2 (Bipolar)			0		\|mV\|
		CLKIN0/1 (MOS)			55
		CLKIN2 (MOS)			20
V_CLKINVIH	High Input Voltage	V_CLKIN-V_IH	DC Coupled Input	2		Vcc	V
V_CLKINVIL	Low Input Voltage	V_CLKIN-V_IL	DC Coupled Input	0		0.4	V
FIN0 Input Pin
f_FIN0	External Input Frequency	AC Coupled Slew Rate > 150 V/us	FIN0_DIV2_EN=1	1		3250	MHz
f_FIN0	External Input Frequency	AC Coupled Slew Rate > 150 V/us	FIN0_DIV2_EN=2	1		6400	MHz
V_IDFIN0	Differential Input Voltage	AC Coupled		0.125		1.55	Vpp
V_SSFIN0	Differential Input Voltage	AC Coupled		0.25		3.1	Vpp
PLL 1 Specifications
f_PD1	Phase Detector Frequency					40	MHz
PN10kHz	PLL Normalized 1/f Noise⁽⁴⁾	PLL1_CP_GAIN = 350 µA			–117		dBc/Hz
PN10kHz	PLL Normalized 1/f Noise⁽⁴⁾	PLL1_CP_GAIN = 1550 µA			–118
PN FOM	PLL Figure of Merit⁽⁵⁾	PLL1_CP_GAIN = 350 µA			–221.5
PN FOM	PLL Figure of Merit⁽⁵⁾	PLL1_CP_GAIN = 1550 µA			–223
I_CPOUT1	Charge Pump Current⁽⁶⁾	VCPout=Vcc/2	PLL1_CP_GAIN=0		50		µA
			PLL1_CP_GAIN=1		150
			PLL1_CP_GAIN=2		250
			PLL1_CP_GAIN=4		450
			PLL1_CP_GAIN=8		850
I_CPOUT1%MIS	Charge Pump Sink / Source Mismatch	V_CPout1 = Vcc/2, T = 25 °C	V_CPout1 = Vcc/2, T = 25 °C		1	10	%
I_CPOUT1V_TUNE	Magnitude of Charge Pump Current Variation vs. Charge Pump Voltage	0.5 V < V_CPout1 < V_CC - 0.5 V T_A = 25 °C	0.5 V < V_CPout1 < V_CC - 0.5 V T_A = 25 °C		1	10	%
I_CPOUT1%TEMP	Charge Pump Current vs. Temperature Varation				2	10	%
I_CPOUT1TRI	Charge Pump TRI_STATE Leakage Current					10	nA
OSCIN Input
f_OSCIN	EN_PLL2_REF_2X=0			0.001		500	MHz
f_OSCIN	EN_PLL2_REF_2X=1			0.001		320	MHz
SLEW_OSCIN	Input Slew Rate			0.15	0.5		V/ns
V_OSCIN	Input voltage for OSCIN_P or OSCIN_N	AC coupled; single-ended; unused pin AC coupled to GND		0.2		2.4	Vpp
V_IDOSCIN	Differential voltage swing⁽³⁾	AC coupled		0.2		1.55	\|V\|
V_SSOSCIN	Differential voltage swing⁽³⁾	AC coupled		0.4		3.1	Vpp
V_CLKINxOffset	DC offset voltage between CLKINx_P/CLKINx_N. Each Pin AC Coupled				20		mV
PLL 2 Specifications
f_PD	Phase Detector Frequency					320	MHz
PN10kHz	PLL Normalized 1/f Noise⁽⁴⁾	PLL2_CP_GAIN = 1600 uA			–123		dBc/Hz
PN10kHz	PLL Normalized 1/f Noise⁽⁴⁾	PLL2_CP_GAIN = 3200 uA			–128
PN FOM	PLL Figure of Merit⁽⁵⁾	PLL2_CP_GAIN = 1600 uA			–226.5
PN FOM	PLL Figure of Merit⁽⁵⁾	PLL2_CP_GAIN = 3200 uA			–230
I_CPOUT	Charge Pump Current Magnitude⁽⁶⁾	V_CPOUT=Vcc/2	PLL2_CP_GAIN=2		1600		µA
I_CPOUT	Charge Pump Current Magnitude⁽⁶⁾	V_CPOUT=Vcc/2	PLL2_CP_GAIN=3		3200		µA
I_CPOUT1%MIS	Charge Pump Sink / Source Mismatch	V_CPOUT = Vcc/2, T = 25 °C	V_CPOUT1 = Vcc/2, T = 25 °C		1	10	%
I_CPout1V_TUNE	Magnitude of Charge Pump Current Variation vs. Charge Pump Voltage	0.5 V < V_CPOUT1 < V_CC - 0.5 V T_A = 25 °C	0.5 V < V_CPOUT1 < V_CC - 0.5 V T_A = 25 °C		2	10	%
I_CPOUT%TEMP	Charge Pump Current vs. Temperature Variation				3	10	%
I_CPOUT1TRI	Charge Pump TRI_STATE Leakage Current					10	nA
Internal VCO Specifications
f_VCO	VCO Frequency Range		VCO0	2440		2600	MHz
f_VCO	VCO Frequency Range		VCO1	2945		3255	MHz
K_VCO	VCO Tuning Sensitivity		VCO0		13		MHz/V
K_VCO	VCO Tuning Sensitivity		VCO1		26		MHz/V
\|ΔT_CL\|	Allowable temperature Drift for Continuous Lock⁽⁷⁾		VCO0			150	^oC
\|ΔT_CL\|	Allowable temperature Drift for Continuous Lock⁽⁷⁾		VCO1			180	^oC
L(f)VCO	Open Loop VCO Phase Noise	VCO0 at 2440 MHz	10 kHz		–88.4		dBc/Hz
			100 kHz		–117
			800 kHz		–137.5
			1 MHz		–139.7
			10 MHz		–152.6
		VCO0 at 2580 MHz	10 kHz		–85.7
			100 kHz		–115.8
			800 kHz		–137
			1 MHz		–138.6
			10 MHz		–151.8
L(f)VCO	Open Loop VCO Phase Noise	VCO1 at 2945 MHz	10 kHz		–82.6		dBc/Hz
			100 kHz		–112.3
			800 kHz		–134.9
			1 MHz		–137.2
			10 MHz		–151.1
		VCO1 at 3250 MHz	10 kHz		–81
			100 kHz		–110.4
			800 kHz		–134.3
			1 MHz		–135.6
			10 MHz		–149.3
Output Clock Skew and Timing
SKEW_CLKOUTX	Output to Output Skew	Same Pair of Device clocks and same format			35		ps
		Even to Even or Odd to Odd, Same Format			15
		Even clock to Odd Clock			35
Additive Jitter in Distribution Mode from FIN Pin (note 6)
L(f)_CLKOUT	Additive jitter, Distribution mode with no divide	245.76 MHz Output Frequency, 12k-20MHz integration bandwidth	LVCMOS		50		fs
			LVDS		50
			LVPECL		40
			LCPECL		35
			HSDS		40
			CML		35
LVCMOS Outputs
f_CLKOUT	Frequency		5 pF Load			250	MHz
L(f)_CLKOUT	Noise Floor	245.76 MHz	20 MHz Offset		–160		dBc/Hz
V_OH	Output High Voltage	1 mA load		Vcc–0.1			V
V_OL	Output Low Voltage	1 mA load				0.1	V
I_OH	Output High Current	FD=1.65V			–28		mA
I_OL	Output Low Current	Vd=1.65V			28		mA
ODC	Output Duty Cycle				50		%
LVDS Clock Outputs
L(f)_CLKOUT	Noise Floor	245.76 MHz output	20 MHz Offset		–159.5		dBc/Hz
T_R/T_F	20% to 80% Rise/Fall Time, f_OUT≥ 1 GHz				175		ps
V_OD	Differential Output Voltage	DC Measurement, AC coupled to receiver input R_L = 100 Ω differential			350		mV
ΔV_OD	Change in V_OD for complimentary output states			–60		60	mV
V_OS	Output Offset Voltage			1.125	1.25	1.375	V
ΔV_OS	Change on VOS for complimentary Output states					35	mV
I_SHORT	Short circuit Output Current			–24		24	mA
LCPECL Clock Outputs
L(f)_CLKOUT	Noise Floor	245.76 MHz output	20 MHz Offset		–162.5		dBc/Hz
T_R/T_F	20% to 80% Rise/Fall Time	f_OUT ≥ 1 GHz			135		ps
V_OH	Output High Voltage	DC Measurement with 50-Ω to 0.5V			1.4		V
V_OL	Output Low Voltage	DC Measurement with 50-Ω to 0.5V			0.6		V
V_OD	Differential Output Voltage	DC Measurement with 50-Ω to 0.5V			870		mV
LVPECL Clock Outputs
L(f)_CLKOUT	Noise Floor	245.76 MHz output, LVPECL 2.0 V	20 MHz Offset		–163		dBc/Hz
T_R/T_F	20% to 80% Rise/Fall Time	f_OUT ≥ 1 GHz			135		ps
V_OH	Output High Voltage	DC Measurement termination 50 Ω to Vcc-2 V	LVPECL 1.6 V		Vcc–1		V
V_OH	Output High Voltage		LVPECL 2.0 V		Vcc–1.1		V
V_OL	Output Low Voltage		LVPECL 1.6 V		Vcc–1.8		V
V_OL	Output Low Voltage		LVPECL 2.0 V		Vcc–2		V
V_OD	Differential Output Voltage	2.5 GHz, Em = 120 Ω to GND, R_L = AC coupled 100 Ω	LVPECL 1.6 V		0.7		V
V_OD	Differential Output Voltage	2.5 GHz, Em = 120 Ω to GND, R_L = AC coupled 100 Ω	LVPECL 2.0 V		0.9		V
HSDS Clock Outputs
L(f)_CLKOUT	Noise Floor	245.76 MHz output	20 MHz Offset		–162		dBc/Hz
T_R/T_F	20% to 80% Rise/Fall Time	f_OUT ≥ 1 GHz			170		ps
V_OH	Output High Voltage	DC Measurement with 50 Ω to 0.5V	HSDS 6 mA		Vcc–0.9		V
V_OH	Output High Voltage		HSDS 8 mA		Vcc–1.0		V
V_OL	Output Low Voltage		HSDS 6 mA		Vcc–1.5		V
V_OL	Output Low Voltage		HSDS 8 mA		Vcc–1.7		V
V_OD	Output Voltage	DC Measurement with 50 Ω to 0.5V	HSDS 6 mA		0.5		V
V_OD	Output Voltage		HSDS 8 mA		0.75		V
ΔV_OD	Change on VOS for complimentary Output states		HSDS 6 mA	–80		80	mV
ΔV_OD	Change on VOS for complimentary Output states		HSDS 8 mA	–115		115	mV
CML Outputs
L(f)_CLKOUT	Noise Floor	20 MHz Offset			–163		dBc/Hz
T_R/T_F	20% to 80% Rise/Fall Time	f_OUT ≥ 1.5 GHz	CML 16 mA		140		ps
			CML 24 mA		140
			CML 32 mA		140
V_OH	Output High Voltage	50 Ω pull up to Vcc, DC Measurement			Vcc-0.1		V
V_OL	Output Low Voltage	50 Ω pull up to Vcc, DC Measurement	CML 16 mA		Vcc–0.8		V
			CML 24 mA		Vcc–1.1
			CML 32 mA		Vcc–1.4
V_OD	Output Voltage	50 Ω pull up to Vcc, DC Measurement	CML 16 mA		680		mV
			CML 24 mA		1000
			CML 32 mA		1300
		50 Ω pull up to Vcc, DC Measurement, R_L = AC coupled 100 Ω, 250 MHz	CML 16 mA		550		mV
			CML 24 mA		815
			CML 32 mA		1070
Digital Outputs (CLKin_SELX,STATUS_LDX, and RESET/GPO,SDIO)
V_OH	Output High Voltage			Vcc–0.4			V
V_OL	Output Low Voltage					0.4	V
Digital Inputs
V_IH	High-level input voltage			1.2			V
V_IL	Low-level input voltage					0.5	V
I_IH	High-level input current	RESET/GPO,SYNC,SCK,SDIO, CS#				80	uA
I_IH	High-level input current	SYNC	V_IH = V_CC			25	uA
I_IL	Low-level input current	CLKINX_SEL,RESET/GPO,SYNC,SCK,SDIO, CS#		–5		5	uA
I_IL	Low-level input current	SYNC	V_IL = 0 V	–5		5	uA

(1) Use the TICS Pro tool to calculate Icc for a specific configuration

(2) Device will function with slew rate as low as 0.15 V/ns, however a slew rate of 0.5 V/ns or higher is recommended to get the best phase noise performance.

(3) See Differential Voltage Measurement Terminology for definition of VID and VOD voltages.

(4) The normalized PLL 1/f noise is a specification in modeling PLL in-band phase noise is that is close to the carrier and has a characteristic 10 dB/decade slope. PN10 kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10 kHz = LPLL_flicker(10 kHz) - 20 log(f_OUT/ 1 GHz), where LPLL_flicker(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can be masked by the reference oscillator performance if a low-power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker(f) and LPLL_flat(f)

(5) The PLL figure of merit is a normalized metric used to quantify the flat portion of the in-band phase noise. It is calculated as PN_FOM = LPLL_flat(f) - 20 log(N) - 10 log(f_PDX). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz bandwidth and f_PDX is the phase detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f). This metric is measured using a CLKIN input. If the OSCin input is used, the metric is about 2 dB worse.

(6) This parameter is programmable to more states than are shown in the electrical specifications

(7) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that the 0x168 register was last programmed with PLL2_FCAL_DIS = 0, and still have the part stay in lock. The action of programming the 0x168 register, even to the same value, activates a frequency calibration routine. This implies the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reload the appropriate register to ensure it stays in lock. This parameter is indirectly tested.