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ZHCSLT2C May 2020 – November 2022 LMK04832-SP

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HBE|64
- MCCF006A

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8.3.2 SYNC/SYSREF

The SYNC and SYSREF signals share the same SYNC/SYSREF Clock Distribution path. To properly use SYNC and/or SYSREF for JESD204B it is important to understand the SYNC/SYSREF system. Figure 8-2 illustrates the detailed diagram of a clock output block with SYNC circuitry included. Figure 8-3 illustrates the interconnects and highlights some important registers used in controlling the device for SYNC/SYSREF purposes.

To reset or synchronize a divider, the following conditions must be met:

SYNC_EN must be set. This ensures proper operation of the SYNC circuitry.
SYSREF_MUX and SYNC_MODE must be set to a proper combination to provide a valid SYNC/SYSREF signal.
- If SYSREF block is being used, the SYSREF_PD bit must be clear.
- If the SYSREF Pulser is being used, the SYSREF_PLSR_PD bit must be clear.
- For each CLKoutX or CLKoutY being used for SYSREF, the respective SCLKX_Y_PD bit must be cleared.
DCLKX_Y_DDLY_PD and SYSREF_DDLY_PD bits must be clear to power up the digital delay circuitry used during SYNC to cause deterministic phase between the device clock dividers and the global SYSREF divider.
The SYNC_DISX bit must be clear to allow SYNC/SYSREF signal to divider circuit. The SYSREF_MUX register selects the SYNC source which resets the SYSREF/CLKoutX dividers provided the corresponding SYNC_DISX bit is clear.
Other bits which impact the operation of SYNC such as SYNC_1SHOT_EN may be set as desired.
After these dividers are synchronized, the DCLKX_Y_DDLY_PD and SYSREF_DDLY_PD bits may be set to save current. Clearing them to power up may disrupt the output clock phase.

Table 8-2 illustrates the some possible combinations of SYSREF_MUX and SYNC_MODE.

Table 8-2 Some Possible SYNC Configurations

NAME	SYNC_MODE	SYSREF_MUX	OTHER	DESCRIPTION
SYNC Disabled	0	0	CLKin0_DEMUX ≠ 0	No SYNC will occur.
Pin or SPI SYNC	1	0	CLKin0_DEMUX ≠ 0	Basic SYNC functionality, SYNC pin polarity is selected by SYNC_POL. To achieve SYNC through SPI, toggle the SYNC_POL bit.
Differential input SYNC	X	0 or 1	CLKin0_DEMUX = 0	Differential CLKin0 now operates as SYNC input.
JESD204B Pulser on pin transition.	2	2	SYSREF_PULSE_CNT sets pulse count	Produce SYSREF_PULSE_CNT programmed number of pulses on pin transition. SYNC_POL can be used to cause SYNC through SPI.
JESD204B Pulser on SPI programming.	3	2	SYSREF_PULSE_CNT sets pulse count	Programming SYSREF_PULSE_CNT register starts sending the number of pulses.
Re-clocked SYNC	1	1	SYSREF operational, SYSREF Divider as required for training frame size.	Allows precise SYNC for n-bit frame training patterns for non-JESD converters such as LM97600.
External SYSREF request	0	2	SYSREF_REQ_EN = 1 Pulser powered up	When SYNC pin is asserted, continuous SYSERF pulses occur. Turning on and off of the pulses is synchronized to prevent runt pulses from occurring on SYSREF.
Continuous SYSREF	X	3	SYSREF_PD = 0 SYSREF_DDLY_PD = 0 SYSREF_PLSR_PD = 1 ⁽¹⁾	Continuous SYSREF signal.
Re-clocked SYSREF distribution	0	0	SYSREF_DDLY_PD = 1 SYSREF_PLSR_PD = 1 SYSREF_PD = 1.	Fan-out of CLKin0 reclocked to the clock distribution path.

(1) SCLKX_Y_PD = 0 as required per SYSREF output. This applies to any SYNC or SYSREF output on SCLKX_Y when SCLKX_Y_MUX = 1 (SYSREF output)

Note:

Because the SYNC/SYSREF signal is reclocked by the Clock Distribution Path, an active clock must be present on the Clock Distribution Path (either from VCO or Fin0/Fin1 pins in distribution mode) for SYNC to take effect.

Note:

Any device clock divider or the SYSREF divider which does not have the SYNC_DISX bit or SYNC_DISSYSREF bit set will reset while SYNC/SYSREF Distribution Path is high. This is especially important for the SYSREF divider which has the ability to reset itself if the SYNC_DISSYSREF = 0! Be sure to set SYNC_DISX/SYNC_DISSYSREF bits as required.

Note:

While using Divide-by-2 or Divide-by-3 for DCLK_X_Y_DIV, SYNC procedure requires to first program Divide-by-4 and then back to Divide-by-2 or Divide-by-3 before doing SYNC.