Digital (coarse) delay allows a group of outputs to be delayed by 8 to 1023 clock distribution path cycles. The delay step can be as small as half the period of the clock distribution path cycle by using the DCLKX_Y_HS bit. There are two different ways to use the digital delay:

1. Fixed digital delay
2. Dynamic digital delay

In both delay modes, the regular clock divider is substituted with an alternative divide value.