Using the clock design tools configuration the TICS Pro software is manually updated with this information to meet the required application.

Frequency planning for assignment of outputs:

• To minimize crosstalk perform frequency planning / CLKout assignments to keep common frequencies on outputs close together.
• It is best to place common device clock output frequencies on outputs sharing the same V_CC group. For example, these outputs share Vcc4_CG2. Refer to Section 5 to see the V_CC groupings the clock outputs.

In this example, the 245.76-MHz ADC output needs the best performance. CLKout2 provides the best noise floor / performance. The 245.76 MHz is placed on CLKout2 with 10.24-MHz SYSREF on CLKout3.

• For best performance the input and output drive level bits may be set. Best noise floor performance is achieved with CLKout2_3_IDL = 1 and CLKout2_3_ODL = 1.
• The CLKoutX_Y_ODL bit has no impact on even clock outputs in high performance bypass mode.

In this example, the 983.04-MHz DAC output is placed on CLKout4 and CLKout6 with 10.24-MHz SYSREF on paired CLKout5 and CLKout7 outputs.

• These outputs share Vcc4_CG2.

In this example, the 122.88-MHz FPGA JESD204B output is placed on CLKout10 with 10.24-MHz SYSREF on paired CLKout11 output.

Additionally, the 122.88-MHz FPGA non-JESD204B outputs are placed on CLKout8 and CLKout9.

• When frequency planning, consider PLL2 as a clock output at the phase detector frequency. As such, these 122.88-MHz outputs have been placed on the outputs close to the PLL2 and Charge Pump power supplies.

Once the device programming is completed as desired in the TICS Pro software, it is possible to export the register settings from the Register tab for use in application.