(1) Use the TICS Pro tool to calculate Icc for a specific configuration.

(2) In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input slew rate is reduced. However, the device will function at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to their common mode noise rejection. However, it is also recommended to use the highest possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs.

(3) See Differential Voltage Measurement Terminology for definition of V_ID and V_OD voltages.

(4) This parameter is programmable

(5) The EN_PLL2_REF_2X bit enables/disables a frequency doubler mode for the PLL2 OSCin path.

(6) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, L_{PLL_flicker}(f), which is dominant close to the carrier. Flicker noise has a 10 dB/decade slope. PN10 kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10 kHz = L_{PLL_flicker}(10 kHz) - 20 log(Fout / 1 GHz), where LPLL_flicker(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure L_{PLL_flicker}(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). L_{PLL_flicker}(f) can be masked by the reference oscillator performance if a low-power or noisy source is used. The total PLL in-band phase noise performance is the sum of L_{PLL_flicker}(f) and L_{PLL_flat}(f).

(7) A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, L_{PLL_flat}(f), is defined as: PN1 HZ = L_{PLL_flat}(f) - 20 log(N) - 10 log(f_PDX). L_{PLL_flat}(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz bandwidth and f_PDX is the phase detector frequency of the synthesizer. L_{PLL_flat}(f) contributes to the total noise, L(f).

(8) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that the 0x168 register was last programmed with PLL2_FCAL_DIS = 0, and still have the part stay in lock. The action of programming the 0x168 register, even to the same value, activates a frequency calibration routine. This implies the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reload the appropriate register to ensure it stays in lock. Regardless of what temperature the part was initially programmed at, the temperature can never drift outside the frequency range of – 40 °C to 85 °C without violating specifications.

(9) Dual Loop, OSCin reference is a 122.88 MHz Crystek 603281 VCXO. Data collected using a MACOM H-183-4 Hybrid Junction for differential to single ended converstion.  PLL2_CP = 3.2 mA.  PLL2 Loop filter is C1i = 60 pF, C1 (external) = 4.7 pF, R2 = 820 Ω (external), C2 = 3.9 nF (external), R3 = 2.4 kΩ, C3 = 50 pF, R4 = 200 Ω, C4 = 10 pF.  PLL1_CP = 450 µA with a narrow loop bandwidth. CLKoutX_Y_IDL = 0, CLKoutX_Y_ODL = 1. Even CLKout with LVPECL20 format using 120-Ω to GND.

(10) OSCout will oscillate at start-up at the frequency of the VCXO attached to OSCin port.

(11) Equal loading and identical clock configuration on each clock input and/or output is required for skew, setup, and hold specifications to be valid.

(12) For OSCout when driven by OSCin, assumes OSCin has 50% input duty cycle.

(13) Even clock outputs (CLKoutX). CLKoutX_Y_IDL=1, CLKoutX_Y_ODL=X.

(14) Odd clock outputs (CLKoutY).  CLKoutX_Y_IDL=X, CLKoutX_Y_ODL=1

(15) LCPECL clocks have 120 Ω emitter resistors.  OSCout LVPECL clock uses 240 Ω ohm emitter resistors.  Other settings include CLKoutX_Y_IDL = 0, CLKoutX_Y_ODL = 0, DCLKX_Y_DCC = 0.  SCLK_X_Y_ADLY_EN = 0.

(16) For even and odd outputs CLKoutX_Y_IDL=0.  For even outputs CLKoutX_Y_ODL=X and for odd CLKoutX_Y_ODL=1.

(17) Even clock outputs (CLKoutX). CLKoutX_Y_IDL=X, CLKoutX_Y_ODL=1.

(18) Odd clock outputs (CLKoutY).  CLKoutX_Y_IDL=X, CLKoutX_Y_ODL=1

(19) CLKoutX_Y_IDL=X and CLKoutX_Y_ODL=X.

(20) Valid for CML 32 mA, CML 24 mA, CML 16 mA.  CML DC bias is 50 ohms to Vcc or 68 nH to 20 Ω to Vcc.

(21) Valid for HSDS 8 mA, HSDS 6 mA, LVDS.  LVPECL20, LVPECL16, LCPECL with 120 Ω emitter resistor to ground.

(22) For any device clock with an odd divide value, assumes selected clock output has DCLKX_Y_DCC = 1 to enable duty cycle correction.

(23) Single Loop, OSCin reference is R&S SMA100B Signal Generator with option SMAB-B711 through Prodyn BIB-100G Balun to OSCin.  Data collected using a MACOM H-183-4 Hybrid Junction for differential to single ended converstion.  PLL2 Loop filter is C1 = 60 pF, R2 = 470 Ω (external), C2 = 150 nF (external), R3 = 2.4 kΩ, C3 = 50 pF, R4 = 200 Ω, C4 = 10 pF, PLL2_CP = 3.2 mA. CLKoutX_Y_IDL = 1, CLKoutX_Y_ODL = 0;  Even CLKout with CML 32 mA format using DC bias 68-nH to 20-Ω to Vcc.