8.1.10 0-Delay

The LMK04832 supports two types of 0-delay.

1. Cascaded 0-delay
2. Nested 0-delay

Cascaded 0-delay mode establishes a fixed deterministic phase relationship of the phase of the PLL2 input clock (OSCin) to the phase of a clock selected by the feedback mux. The 0-delay feedback uses internal feedback from the CLKout6, CLKout8, or SYSREF. The 0-delay feedback can also be from an external feedback through the FBCLKin port. The FB_MUX selects the feedback source. Because OSCin has a fixed deterministic phase relationship to the feedback clock, OSCout will also have a fixed deterministic phase relationship to the feedback clock. In this mode, PLL1 input clock (CLKinX) also has a fixed deterministic phase relationship to PLL2 input clock (OSCin); this results in a fixed deterministic phase relationship between all clocks from CLKinX to the clock outputs.

Nested 0-delay mode establishes a fixed deterministic phase relationship of the phase of the PLL1 input clock (CLKinX) to the phase of a clock selected by the feedback mux. The 0-delay feedback uses internal feedback from the CLKout6, CLKout8, or SYSREF. The 0-delay feedback can also be from an external feedback through the FBCLKin port. The FB_MUX selects the feedback source.

Without using 0-delay mode, there will be n possible fixed phase relationships from clock input to clock output depending on the clock output divide value.

Using an external 0-delay feedback reduces the number of available clock inputs by one.