8.3.4.1.1 Fixed Digital Delay Example

Assuming the device already has the following initial configurations, and the application should delay CLKout2 by one VCO cycle compared to CLKout0.

• VCO frequency = 2949.12 MHz
• CLKout0 = 368.64 MHz (DCLK0_1_DIV = 8, CLKout0_SRC_MUX = 0 (Device Clock))
• CLKout2 = 368.64 MHz (DCLK2_3_DIV = 8, CLKout2_SRC_MUX = 0 (Device Clock))

The following steps should be followed

1. Set DCLK0_1_DDLY = 8 and DCLK2_3_DDLY = 9. Static delay for each clock.
2. Set DCLK0_1_DDLY_PD = 0 and DCLK2_3_DDLY_PD = 0. Power up the digital delay circuit.
3. Set SYNC_DIS0 = 0 and SYNC_DIS2 = 0. Allow the outputs to be synchronized.
4. Perform SYNC by asserting, then unasserting SYNC. Either by using SYNC_POL bit or the SYNC pin.
5. Now that the SYNC is complete, to save power it is allowable to power down DCLK0_1_DDLY_PD = 1 and/or DCLK2_3_DDLY_PD = 1.
6. Set SYNC_DIS0 = 1 and SYNC_DIS2 = 1. Prevent the output from being synchronized, very important for steady-state operation when using JESD204B.

Figure 9. Fixed Digital Delay Example