8.3.4.3 Single and Multiple Dynamic Digital Delay Example

In this example, two separate adjustments are made to the device clocks. In the first adjustment, a single delay of 1 VCO cycle occurs between CLKout2 and CLKout0. In the second adjustment, two delays of 1 VCO cycle occur between CLKout2 and CLKout0. At this point in the example, CLKout2 is delayed 3 VCO cycles behind CLKout0.

Assuming the device already has the following initial configurations:

• VCO frequency: 2949.12 MHz
• CLKout0 = 368.64 MHz, DCLK0_1_DIV = 8
• CLKout2 = 368.64 MHz, DCLK2_3_DIV = 8

The following steps illustrate the example above:

1. Set DCLK2_3_DDLY = 4. First part of delay for CLKout2.
2. Set DCLK2_3_DDLY_PD = 0. Enable the digital delay for CLKout2.
3. Set DDLYd0_EN = 0 and DDLYd2_EN = 1. Enable dynamic digital delay for CLKout2 but not CLKout0.
4. Set DDLYd_STEP_CNT = 1. This begins the first adjustment.

Before step 4, CLKout2 clock edge is aligned with CLKout0.

After step 4, CLKout2 counts nine clock distribution path cycles to the next rising edge, one greater than the divider value, effectively delaying CLKout2 by one VCO cycle with respect to CLKout0. This is the first adjustment.

5. Set DDLYd_STEP_CNT = 2. This begins the second adjustment.

Before step 5, CLKout2 clock edge was delayed 1 clock distribution path cycle from DCLKout0.

After step 5, CLKout2 counts nine clock distribution path cycles twice, each time one greater than the divide value, effectively delaying CLKout2 by two clock distribution path cycles with respect to CLKout0.This is the second adjustment.

Figure 10. Single and Multiple Adjustment Dynamic Digital Delay Example