8.4.1.1 Dual Loop

Figure 15 illustrates the typical use case of the LMK04832 in dual loop mode. In dual loop mode, the reference to PLL1 is from CLKin0, CLKin1, or CLKin2. An external VCXO is used to provide feedback for the first PLL and a reference to the second PLL. This first PLL cleans the jitter with the VCXO by using a narrow loop bandwidth. The VCXO may be buffered through the OSCout port. The VCXO is used as the reference to PLL2 and may be doubled using the frequency doubler. The internal VCO drives up to seven divide/delay blocks which drive up to 14 clock outputs.

Hitless switching and holdover functionality are optionally available when the input reference clock is lost. Holdover works by forcing a DAC voltage to the tuning voltage of the VCXO.

It is also possible to use an external VCO in place of PLL2's internal VCO. In this case one less CLKin is available as a reference as CLKin1 is used for external Fin input.

Figure 15. Simplified Functional Block Diagram for Dual Loop Mode