9.3.8.4 PLL Lock Detectors

The loss-of-lock (LOL) status is available for each APLL and DPLL. The APLLs are monitored for loss-of-frequency lock only. The REF-DPLLs are monitored for both loss-of-frequency lock (LOFL) and loss-of-phase lock (LOPL). The DPLL lock threshold and loss-of-lock threshold are programmable for both LOPF and LOFL detectors.

Each DPLL frequency lock detector will clear its LOFL flag when the DPLL's frequency error relative the selected reference input is less than the lock ppm threshold. Otherwise, it will set the LOFL flag when the DPLL's frequency error is greater than the unlock ppm threshold. The ppm delta between the lock and unlock thresholds provides hysteresis to prevent the LOFL flag from toggling when the DPLL frequency error is crossing these thresholds.

A measurement averaging factor is also used in computing the frequency lock detector register settings. A higher averaging factor increases the measurement delay to set or clear the LOFL flag. Higher averaging may be useful when locking to an input with high wander or when the DPLL is configured with a narrow loop bandwidth. Note that higher averaging reduces the maximum frequency ppm thresholds that can be configured.

Each DPLL phase lock detector will clear its LOPL flag when the DPLL's phase error is less than the phase lock threshold. Otherwise, it will set the LOPL flag when greater than the phase unlock threshold.

The APLL and DPLL lock detector flags can be observed through the status pins and the status bits.

Figure 39. DPLL and APLL Lock Detectors