9.3.9.6.1 VCO Calibration

Each PLL's VCO must be calibrated to ensure that the PLL can achieve lock and deliver optimal phase noise performance. Fundamentally, the VCO calibration establishes an optimal operating point within the tuning range of the VCO. The VCO calibration is executed automatically during initial PLL start-up after device power-on, hard reset, or soft reset once the XO input is detected by its input monitor. To ensure proper VCO calibration, it is critical for the XO clock to be stable in amplitude and frequency prior to the start of VCO calibration; otherwise, the VCO calibration can fail and prevent start-up of the PLL and its output clocks. Prior to VCO calibration and APLL lock, the output drivers are typically held in the mute state (configurable per output) to prevent spurious output clocks.

To trigger VCO calibration for one PLL channel without affecting the other channel, this can be achieved through host programming by either entering/exiting PLL power-down (PLLx_PDN register bit) or by asserting a PLL soft-reset (SWRxPLL register bit).