9.3.17 Zero-Delay Mode (ZDM) Configuration

Zero-delay mode can be enabled to achieve zero phase delay between the selected reference input clock and the output clocks of a DPLL. As shown in Figure 52 and Figure 53, DPLL1 supports zero-delay for OUT4/5, OUT6, and OUT7, while DPLL2 supports zero-delay for OUT0, OUT1, and OUT2/3. Any output that requires the zero-delay feature should be derived from the PLL's P1 (primary) post-divider and have zero-delay enabled (DPLLx_ZDM_EN bit = 1). Then, one of the outputs per DPLL can be selected as the primary zero-delay output (by O_CHx_y_ZERODLY_EN bit). Other outputs that need zero-delay can be synchronized with the primary zero-delay output by comprising a SYNC group (see Output Synchronization (SYNC)). ZDM and DCO mode should not be enabled at the same time within a PLL channel.

When the DPLL is acquiring lock to the reference input, the initial phase lock is governed by the DPLL fastlock bandwidth. Once phase lock is detected, the final output phase alignment with the input reference is governed by the normal DPLL loop bandwidth. The same phase lock and alignment process also occurs when exiting holdover or after a switchover event.

Figure 52. DPLL1 ZDM Configuration for OUT4 to OUT7

Figure 53. DPLL2 ZDM Configuration for OUT0 to OUT3