ZHCSHN9A February 2018 – April 2018 LMK05028
PRODUCTION DATA.
The PLL channel constantly monitors its assigned reference inputs for a valid input clock. When at least one valid input clock is detected, the PLL will exit free-run mode or holdover mode and initiate lock acquisition through the REF-DPLL. The device supports the Fastlock feature where the REF-DPLL temporarily engages a wider loop bandwidth to reduce the lock time. Once lock acquisition is done, the loop bandwidth is set to its normal configured loop bandwidth setting (BWREF-DPLL).