9.4.2.4 Holdover Mode

When a loss of reference (LOR) condition is detected and no valid input is available, the PLL will enter holdover mode. If the tuning word history is valid, the initial output frequency accuracy upon entry into holdover will be pulled to the computed average frequency accuracy just prior to the loss of reference. If no history exists, the holdover frequency accuracy will be determined by the free-run tuning word register (user programmable). The initial holdover frequency accuracy depends on the DPLL loop bandwidth and the elapsed time used for historical averaging. In general, the longer the historical average time, the more accurate the initial holdover frequency assuming the 0-ppm reference clock is drift-free. The stability of the 0-ppm reference clock (either XO or TCXO input) determines the long-term stability and accuracy of the holdover output frequency. Upon entry into holdover, the LOPL flag will be asserted (LOPL → 1); however, the LOFL flag will not be asserted as long as the holdover frequency accuracy does not drift beyond of the programmed loss-of-frequency-lock threshold. When a valid input becomes available for selection, the PLL will exit holdover mode and automatically phase lock with the new input clock without any output glitches.