9.4.6 Cascaded PLL Operation

Each PLL channel has a VCO loopback clock (VCOx FB) routed internally to the input paths of the opposite DPLLs to support PLL cascading, where the VCO loopback clock from the first PLL stage (either PLL1 or PLL2) is used as an input reference to the second PLL stage. PLL cascading allows the second PLL must be precisely locked to the frequency of the first PLL. The internal VCO loopback configuration options are implemented identically on both PLL channels, allowing PLL2 to be cascaded after PLL1 or vice versa. The loopback configuration options include programmable VCO clock dividers, clock muxes to loop-back to either REF-DPLL or TCXO-DPLL inputs, and loopback clock validation to control the PLL lock sequence for the second PLL stage. The internal VCO loopback option eliminates the need for external clock loopback, which would otherwise require the designer to dedicate an output buffer, an input buffer, and external routing to support cascaded PLL operation. See PLL Cascading With Internal VCO Loopback.