The missing pulse monitor uses a window detector to validate input clock pulses that arrive within the nominal clock period plus a programmable late window threshold (T_LATE). When an input pulse arrives before T_LATE, the pulse is considered valid and the missing pulse flag will be cleared. When an input pulse does not arrive before T_LATE (due to a missing or late pulse), the flag will be set immediately to disqualify the input.

Typically, T_LATE should be set higher than the longest clock period (including cycle-to-cycle jitter) of the input, or higher than the gap width for a gapped clock. The missing pulse monitor can act as a coarse frequency detector with faster detection than the ppm frequency detector. The missing pulse monitor is supported for input frequencies between 2 kHz and f_VCO1/12 and should be disabled when outside this range.

The missing pulse and runt pulse monitors operate from the same window detector block for each reference input. The status flags for both these monitors are combined by logic-OR gate and can be observed through status pin. The window detector flag for the selected DPLL input can also be observed through the corresponding MISSCLK status bit.