Each APLL VCO must be calibrated to ensure that the PLL can achieve lock and deliver optimal phase noise performance. VCO calibration establishes an optimal operating point within the VCO tuning range. VCO calibration is executed automatically during initial PLL start-up after device power-on, hard-reset, or soft-reset once the XO input is detected by its input monitor. To ensure successful calibration and APLL lock, it is critical for the XO clock to be stable in amplitude and frequency before the start of calibration; otherwise, the calibration can fail and prevent PLL lock and output clock start-up. Before VCO calibration and APLL lock, the output drivers are typically held in the mute state (configurable per output) to prevent spurious output clocks.

A VCO calibration can be triggered manually for a single APLL by toggling a PLL power-down cycle (PLLx_PDN bit = 1 → 0) through host programming. This may be needed after the APLL N divider value (VCO frequency) is changed dynamically through programming.